I/O Organization

Peripheral Devices / Input-Output devices

• Peripheral devices are external or internal hardware components that
expand the functionality of a computer system by enabling
communication with the central system and external environments.
• The most common input output devices are: Monitor, Keyboard,
Mouse, Printer, Magnetic tape.
• Input Output Interface provides a method for transferring information
between internal storage and external I/O devices.
• Peripherals connected to a computer need special communication
links for interfacing them with the central processing unit.
• The purpose of communication link is to resolve the differences that
exist between the central computer and each peripheral.
The Major Differences
• Peripherals are electromechanical and electromagnetic devices and
CPU and memory are electronic devices.
• Therefore, a conversion of signal values may be needed.
• The data transfer rate of peripherals is usually slower than the
transfer rate of CPU and consequently, a synchronization mechanism
may be needed.
• Data codes and formats in the peripherals differ from the word
format in the CPU and memory.
• The operating modes of peripherals are different from each other and
must be controlled so as not to disturb the operation of other
peripherals connected to the CPU.
• To resolve these differences, computer systems include special
hardware components between the CPU and Peripherals to
supervises and synchronizes all input and out transfers.
• These components are called Interface Units because they interface between
the processor bus and the peripheral devices.
I/O modules
• I/O modules has two major functions:
1. Interface to the CPU and memory via system bus
2. Interface to one or more I/O devices by tailored data links
Major Requirement of an I/O module
1. Control and timing
2. CPU communication
3. Device communication
4. Data buffering
5. Error Detection
• The I/O module includes a control and timing requirements to
coordinate the flow of traffic between internal resources (memory ,
system bus) and external devices.
• The I/O Bus consists of
• data lines, address lines and control lines.
• CPU sends commands to the I/O module which are generally the
control signals on the control bus.
• Exchange of data between the CPU and the I/O module over the data
bus.
• The data transfer rate of peripherals is often much slower than that of
the CPU. So it is necessary to check whether peripheral is ready or not
for data transfer
• If not, CPU must wait.
• So it is important to know the status of I/O module.
• The status signals such as BUSY,READY can be used for this purpose.
• Number of peripheral devices may be connected to the I/O module.
• The I/O bus from the processor is attached to all peripherals interface.
• To communicate with a particular device, the processor places a device
address on address lines.
• Each Interface decodes the address and control received from the I/O bus,
interprets them for peripherals and provides signals for the peripheral
controller.
• The data coming from memory or CPU are sent to an I/O module ,
buffered and then sent to the device at its data rate.
• I/O module is also responsible for error detection anf for reporting
error to the CPU.
Programmed I/O Mode:
• I/O operations will mean a data transfer between an I/O device and
memory or between an I/O device and the CPU.
• If in any computer system I/O operations are completely controlled by
the CPU , then that system is said to be Programmed I/O.
• In this mode of data transfer the operations are the results in I/O
instructions which is a part of computer program.
• Each data transfer is initiated by an instruction in the program. Normally
the transfer is from a CPU register to peripheral device or vice- versa.
• Once the data is initiated the CPU starts monitoring the interface to see
when next transfer can made.
• The instructions of the program keep close tabs on everything that takes
place in the interface unit and the I/O devices.
• The transfer of data requires three instructions:
• Read the status register.
• Check the status of the flag bit and branch to step 1 if not set or to step 3 if
set.
• Read the data register.

• In this technique CPU is responsible for executing data from the memory for
output and storing data in memory for executing of Programmed I/O as
shown in Fig.
Drawback of the Programmed I/O
• The main drawback of the Program Initiated I/O was that the CPU has
to monitor the units all the times when the program is executing.
• Thus, the CPU stays in a program loop until the I/O unit indicates that
it is ready for data transfer.
• This is a time-consuming process and the CPU time is wasted a lot in
keeping an eye to the executing of program.
Interrupt-Initiated I/O
• Interrupts are signals that inform the processor of an event requiring
immediate attention.
• In this method an interrupt facility an interrupt command is used to inform
the device about the start and end of transfer.
• In the meantime, the CPU executes other program.
• When the interface determines that the device is ready for data transfer it
generates an Interrupt Request and sends it to the computer.
• When the CPU receives such signal, it temporarily stops the execution of
the program and branches to a service program to process the I/O transfer
and after completing it returns back to task, what it was originally
performing.
• In this type of IO, computer does not check the flag. It continues to
perform its task.
• Whenever any device wants the attention, it sends the interrupt
signal to the CPU.
• CPU then deviates from what it was doing, store the return address
from PC and branch to the address of the subroutine.
• I/O interrupts can be classified into vectored and non-vectored
interrupts based on how the interrupt service routine (ISR) address is
determined.
Vectored Interrupt
• A vectored interrupt is one where the address of the interrupt
service routine (ISR) is predefined or provided by the interrupting
device.
• The CPU automatically gets the address of the ISR.
• The address may be hardcoded in the processor or provided by an interrupt
vector table (IVT).
• Faster as it directly jumps to the ISR.
Non-Vectored Interrupt
• A non-vectored interrupt is one where the address of the ISR is not
predefined. Instead, the CPU must request or fetch the ISR address
from the interrupting device or handle it in a generic way.
• The CPU does not automatically know the ISR address.
• It must execute a common interrupt service routine that determines the
correct ISR.
• Slightly slower due to extra processing.
• There are two main drawbacks in both the techniques , programmed
I/O and Interrupt driven I/O :
• The I/O transfer rate is limited by the speed with which the CPU can test and
service a device.
• The time that the CPU spends testing the I/O device status and executing a
number of instructions for I/O data transfers can often be better spent on
other processing tasks.
Direct Memory Access (DMA)
• Direct Memory Access (DMA) is a technique in computer systems
that allows certain hardware components (like disk drives, network
cards, or GPUs) to transfer data directly to or from memory without
involving the CPU for every byte of data.
• This improves system performance by freeing up the CPU to perform other
tasks while data transfer occurs in the background.
• The external device which controls the data transfer is referred to as
DMA controller
Direct Memory Access (DMA)
• In the Direct Memory Access (DMA)
the interface transfer the data into
and out of the memory unit through
the memory bus.
• The transfer of data between a fast
storage device such as magnetic disk
and memory is often limited by the
speed of the CPU.
• Removing the CPU from the path and
letting the peripheral device manage
the memory buses directly would
improve the speed of transfer.
• This transfer technique is called
Direct Memory Access (DMA).
• During the DMA transfer, the CPU is idle and has no control of the memory
buses.
• A DMA Controller takes over the buses to manage the transfer directly
between the I/O device and memory.
• The CPU may be placed in an idle state in a variety of ways. One common
method extensively used in microprocessor is to disable the buses through
special control signals such as:
• Bus Request (BR)
• Bus Grant (BG)
DMA Controller
• DMA Controller:
• The DMA controller needs the usual circuits of an interface to communicate
with the CPU and I/O device. The DMA controller has three registers:
• Address Register
• Word Count Register
• Control Register
• Address Register:
• Address Register contains an address to specify the desired location in
memory.
• Word Count Register:
• WC holds the number of words to be transferred. The register is incre/decre
by one after each word transfer and internally tested for zero.
• Control Register:
• Control Register specifies the mode of transfer
• The unit communicates with the CPU via the data bus and control
lines.
• The registers in the DMA are selected by the CPU through the address
bus by enabling the DS (DMA select) and RS (Register select) inputs.
• The RD (read) and WR (write) inputs are bidirectional.
• When the BG (Bus Grant) input is 0, the CPU can communicate with
the DMA registers through the data bus to read from or write to the
DMA registers.
• When BG =1, the DMA can communicate directly with the memory by
specifying an address in the address bus and activating the RD or WR
control.
• These two control signals (BR,BG) in the CPU that facilitates the DMA
transfer.
• The Bus Request (BR) input is used by the DMA controller to request
the CPU.
• When this input is active, the CPU terminates the execution of the current
instruction and places the address bus, data bus and read write lines into a
high Impedance state.
• High Impedance state means that the output is disconnected.
• The CPU activates the Bus Grant (BG) output to inform the external
DMA that the Bus Request (BR) can now take control of the buses to
conduct memory transfer without processor.
• When the DMA terminates the transfer, it disables the Bus Request
(BR) line.
• The CPU disables the Bus Grant (BG), takes control of the buses and
return to its normal operation.
DMA Transfer
• The CPU communicates with the DMA through the address and data
buses as with any interface unit.
• The DMA has its own address, which activates the DS and RS lines.
The CPU initializes the DMA through the data bus.
• Once the DMA receives the start control command, it can transfer
between the peripheral and the memory.
• When BG = 0 the RD and WR are input lines allowing the CPU to
communicate with the internal DMA registers. When BG=1, the RD
and WR are output lines from the DMA controller to the random
access memory to specify the read or write operation of data.
• The transfer can be made in several ways that are: (8257A DMA)
• Burst Mode (Block Transfer Mode)
• Cycle Stealing Mode (Single Transfer Mode)
• Demand Transfer Mode
• Cascade Mode
• Burst Transfer Mode:
• In DMA Burst transfer, a block sequence consisting of a number of memory
words is transferred in continuous burst while the DMA controller is master of
the memory buses.
• Cycle Stealing Mode:
• Cycle stealing allows the DMA controller to transfer one data word at a time,
after which it must returns control of the buses to the CPU.
• Demand Transfer Mode:
• Demand Transfer Mode is a DMA mode where the transfer occurs only when
the peripheral device is ready and requests data. The transfer pauses if the
device is not ready and resumes when it signals readiness again.
• Cascade Mode:
• Cascade Mode is used when multiple DMA controllers are connected in a
system, allowing one controller to act as a master while others function as
slaves. It enables the expansion of DMA channels.