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Lab 7

The document outlines an experiment aimed at interfacing an Analog to Digital Converter (ADC) with an ARM processor using assembly language in Keil UV4 software. It details the necessary materials, software requirements, and procedures for executing the program, as well as the architecture and registers of the ADC in the LPC2148. Additionally, it includes sample assembly code for ADC interfacing and pre- and post-lab questions related to the experiment.

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0% found this document useful (0 votes)
10 views7 pages

Lab 7

The document outlines an experiment aimed at interfacing an Analog to Digital Converter (ADC) with an ARM processor using assembly language in Keil UV4 software. It details the necessary materials, software requirements, and procedures for executing the program, as well as the architecture and registers of the ADC in the LPC2148. Additionally, it includes sample assembly code for ADC interfacing and pre- and post-lab questions related to the experiment.

Uploaded by

nayansoni306
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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7 ANALOG TO DIGITAL CONVERTER INTERFACING WITH ARM

PROCESSOR

7.1. Aim(s) / Objective(s) / Purpose


The purpose of this experiment is to write assembly language programming to interface the
analog to digital converter with ARM processor in Keil UV4 software.
7.2 Introduction / Background
The purpose of this experiment is to perform the simulation of analog to digital converter with ARM
processor using assembly language programming in Keil environment.

7.3 Materials / Equipment

1.​ Andrew Sloss, Dominic Symes, and Chris Wright. ARM system developer's guide: designing and
optimizing system software. Elsevier, 2004.
2.​ Mazidi, M., Naimi, S., Naimi, S. and Mazidi, J., ARM Assembly Language Programming &
Architecture. y Pearson Education, Inc., 2013.

7.4 Software Requirement:


​ KEIL UV4 with supported device packages installed.

7.5 Procedure
i)​ Enter the PROGRAM
ii)​ Execute the program
iii)​ Check for the result in destination.

ADC (Analog to Digital Converter) in ARM LPC2148
Analog to Digital Converter (ADC) is used to convert analog signal into digital form. LPC2148 has
two inbuilt 10-bit ADC i.e. ADC0 & ADC1.
1. ADC0 has 6 channels & ADC1 has 8 channels.
Hence, we can connect 6 distinct types of input analog signals to ADC0 and 8 distinct types of input
analog signals to ADC1.
2. ADCs in LPC2148 use Successive Approximation technique to convert analog signal into digital
form.
3. This Successive Approximation process requires a clock less than or equal to 4.5 MHz. We can
adjust this clock using clock divider settings.
4. Both ADCs in LCP2148 convert analog signals in the range of 0V to VREF (typically 3V; not to
exceed VDDA voltage level).
*AD0.1:4, AD0.6:7 & AD1.7:0 (Analog Inputs)
These are Analog input pins of ADC. If ADC is used, signal level on analog pins must not be above
the level of VDDA;
otherwise, ADC readings will be invalid. If ADC is not used, then the pins can be used as 5V tolerant
digital I/O pins.
VREF (Voltage Reference)
Provide Voltage Reference for ADC.
VDDA& VSSA (Analog Power and Ground)
These are the power and ground pins for ADC. These should be same as VDD & VSS.
REGISTERS OF ADC:
1. AD0CR (ADC0 Control Register)
●​ AD0CR is a 32-bit register.
●​ This register must be written to select the operating mode before A/D conversion can occur.
●​ It is used for selecting channel of ADC, clock frequency for ADC, number of clocks or
number of bits in result, start of conversion and few other parameters.
Bits 7:0 – SEL
These bits select ADC0 channel as analog input. In software-controlled mode, only one of these bits
should be 1.e.g. bit 7 (10000000) selects AD0.7 channel as analog input.
00000010 - AD0.1 Channel
00000100 - AD0.2 Channel
00001000 - AD0.3 Channel
Bits 15:8 – CLKDIV
The APB (ARM Peripheral Bus) clock is divided by this value plus one, to produce the clock for
ADC.
This clock should be less than or equal to 4.5MHz.
Bit 16 – BURST
0 = Conversions are software controlled and require 11 clocks
1 = In Burst mode ADC does repeated conversions at the rate selected by the CLKS field for the
analog inputs
selected by SEL field. It can be terminated by clearing this bit, but the conversion that is in progress
will be completed.
When Burst = 1, the START bits must be 000, otherwise the conversions will not start.
Bits 19:17 – CLKS
Selects the number of clocks used for each conversion in burst mode and the number of bits of
accuracy of Result bits of AD0DR.
e.g. 000 uses 11 clocks for each conversion and provide 10 bits of result in corresponding ADDR
register.
000 = 11 clocks / 10 bits
001 = 10 clocks / 9 bits
010 = 9 clocks / 8 bits
011 = 8 clocks / 7 bits
100 = 7 clocks / 6 bits
101 = 6 clocks / 5 bits
110 = 5 clocks / 4 bits
111 = 4 clocks / 3 bits
Bit 20 – RESERVED
Bit 21 – PDN
0 = ADC is in Power Down mode
1 = ADC is operational
Bit 23:22 – RESERVED
Bit 26:24 – START
When BURST bit is 0, these bits control whether and when A/D conversion is started
000 = No start (Should be used when clearing PDN to 0)
001 = Start conversion now
010 = Start conversion when edge selected by bit 27 of this register occurs on CAP0.2/MAT0.2 pin
011= Start conversion when edge selected by bit 27 of this register occurs on CAP0.0/MAT0.0 pin
100 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.1 pin
101 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.3 pin
110 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.0 pin
111 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.1 pin
Bit 27 – EDGE
This bit is significant only when the Start field contains 010-111. In these cases,
0 = Start conversion on a rising edge on the selected CAP/MAT signal
1 = Start conversion on a falling edge on the selected CAP/MAT signal
Bit 31:28 – RESERVED
2. AD0GDR (ADC0 Global Data Register)
AD0GDR is a 32-bit register.
This register contains the ADC’s DONE bit and the result of the most recent A/D conversion.
Bit 5:0 – RESERVED
Bits 15:6 – RESULT
When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the
range of 0 (less than or equal to VSSA) to 1023 (greater than or equal to VREF).
Bit 23:16 – RESERVED
Bits 26:24 – CHN
These bits contain the channel from which ADC value is read.
e.g. 000 identifies that the RESULT field contains ADC value of channel 0.
Bit 29:27 – RESERVED
Bit 30 – Overrun
This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten
before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
Bit 31 – DONE
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and
when the AD0CR is written.
If AD0CR is written while a conversion is still in progress, this bit is set and new conversion is
started.

7.6 PROGRAMS:
Program 1: TO PERFORM ADC INTERFACING WITH LPC2148 (ARM PROCESSOR)
USING ARM ASSEMBLY LANGUAGE INSTRUCTIONS

ADDRES LABEL MNEMONICS OPCODE COMMENTS


S
AREA ADCCONV, CODE,
READONLY
PINSEL1 EQU 0xE002C004

AD0CR EQU 0xE0034000

AD0GDR EQU 0xE0034004

LDR R1, =PINSEL1

LDR R2, =0x15000000

STR R2, [R1]

LDR R1, =AD0CR

LDR R2, =0x01200102

STR R2, [R1]


L LDR R3, =AD0GDR​

LDR R4, [R3]

LDR R1, =0x80000000

AND R1, R4

LDR R5, =0x80000000

CMP R1, R5

BNE L

LDR R4, [R3]

LDR R1, =0x0000FFC0

AND R7, R1, R4

LSR R8, R7, #6

LDR R1, =AD0CR

LDR R2, =0x01200104

STR R2, [R1]

LP LDR R3, =AD0GDR

LDR R4, [R3]

AND R1, R4

LDR R5, =0x80000000

CMP R1, R5

BNE LP

LDR R4, [R3]

LDR R1, =0x0000FFC0

AND R7, R1, R4


LSR R9, R7, #6

LDR R1, =AD0CR

LDR R2, =0x01200108

STR R2, [R1]

La LDR R3, =AD0GDR

LDR R4, [R3]

LDR R1, =0x80000000​

AND R1, R4

LDR R5, =0x80000000

CMP R1, R5

BNE La

LDR R4, [R3]

LDR R1, =0x0000FFC0

AND R7, R1, R4

LSR R10, R7, #6

L1 B L1

END

PRE-LAB QUESTIONS:
1.​ Write the steps involved for analog to digital conversion in ARM LPC2148 MCU.
2.​ Draw the register formats for analog to digital converter global start register (ADGSR) and analog
to digital converter status register (AD0STAT).
POST-LAB QUESTIONS:
1.​ Describe any four applications of analog to digital converter?
2.​ How to activate the ADC to operate in low power mode in LPC2148.
Result:

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