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NPTEL CC Assignment0

The document is an assignment for a Cloud Computing course containing 10 multiple-choice questions (MSQ) with detailed solutions. It covers topics such as cache access times, port numbers, memory operations, CPU data paths, IP datagram fields, OSI model layers, subnetting, classful addressing, and cache directory sizes. Each question includes the correct answer and a brief explanation of the solution.

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Sudhakar Uppalapati
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21 views6 pages

NPTEL CC Assignment0

The document is an assignment for a Cloud Computing course containing 10 multiple-choice questions (MSQ) with detailed solutions. It covers topics such as cache access times, port numbers, memory operations, CPU data paths, IP datagram fields, OSI model layers, subnetting, classful addressing, and cache directory sizes. Each question includes the correct answer and a brief explanation of the solution.

Uploaded by

Sudhakar Uppalapati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Cloud Computing

Assignment- Week 0
TYPE OF QUESTION: MSQ

Number of questions: 10 Total mark: 10 X 1 = 10

QUESTION 1:
Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache, and main
memory are 2 ns, 12 ns, and 120 ns, respectively. The hit rates of Level 1, Level 2 cache, and main
memory are 0.4, 0.6, and 1.0 respectively. What is the average access time of the system ignoring
the search time within the cache?

a) 39.32 ns
b) 33.92 ns
c) 32.93 ns
d) 39.32 ms

Correct Answer: b

Detailed Solution: Average access time = [H1*T1]+[(1-H1)*H2*T2]+[(1-H1)(1-H2)*Hm*Tm]


H1 = Hit rate of level 1 cache = 0.4
T1 = Access time for level 1 cache = 2 ns
H2 = Hit rate of level 2 cache = 0.6
T2 = Access time for level 2 cache = 12 ns
Hm = Hit rate of Main Memory = 1.0
Tm = Access time for Main Memory = 120 ns

QUESTION 2:
Which of the following port can be used by a user defined program?
a) 1002
b) 47021
c) 60535
d) 65564

Correct Answer: c
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Detailed Solution: The Internet Assigned Numbers Authority (IANA) and RFC 6335 suggests the
range 49152–65535 for dynamic or private ports. Maximum possible port number is 65535.

QUESTION 3:
The memory locations 5000, 5001 and 5020 have data values 118, 101 and 116 respectively
before the following program is executed.

MOVI R1, 1

LOAD R2, 5000(R1)

ADDI R2, 5000

STOREI 0(R2), 77

Which of the statements below is TRUE after the program is executed?

a) Memory location 5000 has value 77


b) Memory location 5020 has value 77
c) Memory location 5001 has value 77
d) Memory location 5101 has value 77

Correct Answer: d

Detailed Solution:
1. R1←1 (Move immediate)
2. R2←[5000+[R1]], ( Load from memory)
R2←5000+1
[5000+1]=101
Thus, value =101 is moved to the register R2
3. R2←101+5000 (Add Immediate)
4. 77 will be stored to 0+5101 (Store immediate)
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Indian Institute of Technology Kharagpur

QUESTION 4:

In the above-mentioned data path of a CPU, it is given; all the components of the data path are of
identical sizes. ALU carries out all the operations including the incrementation of PC as well as
GPRs. It needs two clock cycles to complete a memory read operation. For the instruction “add Rs,
Rd”, which of the following statements is correct?

a) At least three clock cycles are needed to complete the execution cycle of the instruction.
b) At least five clock cycles are needed to complete the execution cycle of the instruction.
c) At least two clock cycles are needed to complete the execution cycle of the instruction.
d) At least four clock cycles are needed to complete the execution cycle of the instruction.

Correct Answer: a

Detailed Solution: 1st clock cycle for Rs to S


2nd clock cycle for Rd to T
3rd clock cycle for add operation meansRs + Rd So
for execution only 3 cycles are required.

QUESTION 5:
The interrupt-request line is a part of the ___________
a. Data line
b. Address line
c. Control line
d. None of these
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Indian Institute of Technology Kharagpur

Correct Answer: c

Detailed Solution: The Interrupt-request line is a control line along which the device is allowed to
send the interrupt signal.

QUESTION 6:
One of the header fields in an IP datagram is the Time to Live (TTL) field. Which of the following
statements best explains the need for this field?

a) It can be used to prioritize packets


b) It can be used to reduce delays
c) It can be used to optimize throughput
d) It can be used to prevent packet looping

Correct Answer: d

Detailed Solution: Time to Live can be thought as an upper bound on the time that an IP
datagram can exist in the network. The purpose of the TTL field is to avoid a situation in which an
undeliverable datagram keeps circulating.

QUESTION 7:

Which of the following is wrong concerning to the OSI model?


a) File transfer protocol (FTP) is a part of transport layer
b) Transmission control protocol (TCP) is a part of transport layer
c) User datagram protocol (UDP) is a part of transport layer
d) None of the above

Correct Answer: a

Detailed Solution: TCP and UDP are part of transport layer of OSI model whereas FTP is a part of
application layer
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Indian Institute of Technology Kharagpur

QUESTION 8:
If a class B network on the Internet has a subnet mask of 255.255.240.0, what is
the maximum number of hosts per subnet?
a) 4096
b) 4094
c) 2046
d) 2048

Correct Answer: b
Detailed Solution: The binary representation of the subnet mask is
1111111.11111111.11110000.00000000. There are 20 bits set in the subnet. So 12 (32-20) bits are
left for host ids. Total possible values of host ids is 2^12 = 4096. Out of these 4096 values, 2
addresses are reserved. The address with all bits as 1 is reserved as broadcast address and
address with all host id bits as 0 is used as the network address of the subnet. In general, the
number of addresses usable for addressing specific hosts in each network is always 2^N – 2 where
N is the number of bits for host id.

QUESTION 9:
In classful addressing, an IP address 244.223.156.41 belongs to _____ format.
a) Class A
b) Class B
c) Class C
d) Class D

Correct Answer: d
Detailed Solution: 0 - 126 = Class A
128 - 191 = Class B
192 - 223 = Class C
224 - 255 = Class D
So ans is D.

QUESTION 10:
A computer’s processor sends 32 bit addresses to the cache controller. It has a 512 KByte, 8-way
set associative, write back data cache with block size of 32 Bytes. In addition to the address tag,
each cache tag directory entry contains 3 valid bits and 1 modified bit. Find the size of the cache
tag directory.
a) 212 Kbits
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b) 320 Kbits
c) 160 Kbits
d) 120 Kbits

Correct Answer: b

Detailed Solution: Number of blocks = Cache-Size/Block-Size = 512 KB / 32 Bytes = 214


Number of Sets = 214 / 8 = 211
Tag + Set offset + Byte offset = 32
Tag + 11 + 5 = 32
Tag = 16
16 bit address
3 bit valid
1 modified
Total bits = 20
20 × no. of blocks = 320 K bits.

************END***********

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