ELEC2022

State Machines

The outputs of a FF depend on the present state of the FF rather than the inputs at any point in time. It
is important to realize that the inputs cause changes in state.

In sequential circuits, the outputs depend on the past behavior of the circuit as well as the present
inputs. A clock is used to cause changes in state. These circuits are called synchronous sequential circuits
or Finite State Machines (FSM) and Figure 1 shows the general design.

Figure 1: Synchronous sequential circuit Mealy and Moore type

In the Mealy model, the output is a function of both the present state and the input. In the
Moore model, the output is a function of only the present state. A circuit may have both types
of outputs. The two models of a sequential circuit are commonly referred to as a finite state
machine, abbreviated FSM.
The circuit presented previously and repeated below is an example of a Mealy machine. Output
y is a function of both input x and the present state of A and B . The corresponding state
diagram shows both the input and output values, separated by a slash along the directed lines
between the states.
 Mealy machine

An example of a Moore model is shown. The output depends only on flip-flop values, and that
makes it a function of the present state only. The input value in the state diagram is labeled
along the directed line, but the output value is indicated inside the circle together with the
present state.

Moore machine
State Reduction

The reduction in the number of flip-flops in a sequential circuit is referred to as the state-
reduction problem. State-reduction algorithms are concerned with procedures for reducing the
number of states in a state table, while keeping the external input–output requirements
unchanged. Since m flip-flops produce 2m states, a reduction in the number of states may (or
may not) result in a reduction in the number of flip-flops and may make the corresponding
circuit simpler.

Example The state diagram has 7 states that

To reduce the number of states we look for two present states that go to the same next state
and have the same output for both input combinations. States e and g are two such states:
They both go to states a and f and have outputs of 0 and 1 for x = 0 and x = 1, respectively.
Therefore, states g and e are equivalent, and one of these states can be removed. The new
state table is shown

Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1, respectively.
The same next states and outputs appear in the row with present state d .Therefore, states f
and d are equivalent, and state f can be removed and replaced by d as shown.
This will give a reduced state diagram

The State Machine

A logic circuit counts the number of 1’s in a serial bit stream. When the input bit stream contains an odd
number of 1’s and the output is asserted it is called an odd parity checker. If the output is asserted when
the input has an even number of 1’s it is an even parity checker. This ckt. is sequential as the current
output depends on the past inputs. It has two states: either an odd or an even number of 1’s.

A state diagram can be constructed as follows: At reset it is assumed that the state is even and the
output is 0. When the state is odd the output is 1. When in the even state, and a 0 occurs there is no
change in state. If the input is 1 then there will be an odd number of 1’s and the next state is odd.

Encode the state table by assigning unique coded binary values to the state names. Note that if there
are only two states only one binary value is used. If there are 3-4 states two bits are used, 5-8 states 3
bits are used etc.
 State Diagram State Transition Table

From the above State transition table, it is seen that the Next State =Present state  Input and the
Output = Present State. Using D FFs derive the circuit diagram

Design Approach

1. From the word description and specifications of the desired operation, derive a state diagram
for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram.

Design a circuit that meets the following specifications:

The design procedure:

`
Using JK FFs
Designing with T flip flops

Complete design.
Question

1. An electronic lock has three buttons: "Reset", "0" and "1". A state diagram for the lock is
shown:

The lock makes a transition from its current state to the next state whenever one of the
three buttons is pressed and released. More than one simultaneous button press is
ignored. Pressing ‘Reset’ always returns the lock to state R. Pressing "0" or "1" will
cause the lock to move to a next state. The lock opens if it reaches the state "U".

a. After pressing the "Reset" button what is the length of the shortest sequence of button
presses that will open the lock?
b. After pressing the "Reset" button what is the length of the longest sequence of button
presses that will cause the lock to open after the last button in the sequence is pressed
but not open any earlier in the sequence?
c. The "Reset" button has malfunctioned. Is it still possible to open the lock using only the
"0" and "1" buttons. Give the sequence that opens the lock.
d. Suppose a lock is required that opens exactly 10 button presses after pressing "Reset".
What is the minimum number of state the FSM would need (including Reset and
Unlock.)?