HW 1

紙本作業繳交時間: 3/21, 3pm 前， 工學院七樓 E0708 實驗室

Q1
Calculate the bias current of M1 in Fig. 1. Assume μnCox = 100 μA/V2 and VTH =
0.4 V. If the gate voltage increases by 10 mV, what is the change in the drain voltage?
Id =
MnCoxE (Vos - Vi) EX100 10 x 11 01 43" Vd Upp-In x5 103 1 8 1 0336 0766
= x .
-
0 .

,
= x = .
-
.
=
&

8 766
034#
0 0 =
0
Q2
=
. .
.

Determine the value of W/L in Fig. 1 that places M1 at the edge of saturation and
calculate the drain voltage change for a 1 mV change at the gate. Assume VTH = 0.4
V. Saturation VDs ? Vos- VT :

VDD-IDRD21-0 .
4

1 8 .
- IDX5x1020 .
6

# ? ID

156 x * (0 6)
= 0 5 x 100 x
.
x .

, I =

Vos 1 - 1001 ,
VasIoVod => Triode

= 5x100Xx(060-E) 0.

VD = 0 . 5949V
0 .
6 -
0 .
5949 = 0 . 005/V
Fig. 1 #

Q3
A MOSFET is biased at a drain current of 0.5 mA. If μnCox = 100 μA/V2, W/L = 10,
and λ = 0.1 V−1, calculate its small-signal parameters gm and ro. (Ignore the λVDS).
&m Moxt (
== +100x10 10x05x103
= x
103(s) Vo == = xio =
,
: 2x10tm

Q4 Construct the small-signal model of the circuits depicted in Fig. 2(a)-(c). Assume
all transistors operate in saturation and λ0.

(v) Fig. 2

n
Fu
given
=

o t
(b)
EnT Vote

me
Q5 a vo

Calculate the voltage gain of the circuits depicted in Fig. 3. Assume λ = 0.

me
Fig. 3
i
Vin =
Vysl +
gm Vgs
,
, mu