1. Describe various input & output ports of AXI protocol?

The AXI protocol is structured around five channels, each with its own set of input and output ports. These
channels are:
Read Address Channel : -
ARADDR: Read address specifies the address of the data to be read.
ARID: Read address ID. identification of the read transaction.
ARLEN: Burst length. specifies the number of data transfers in the burst.
ARSIZE: Burst size. specifies the size of each data transfer.
ARBURST: Burst type. determines how the address for each transfer within the burst is calculated.
ARLOCK: Lock Type. Output port that provides the lock status information.
ARCACHE: Cache Type. Output port that carries the cache type information.
ARPROT: Protection Type. Output port that provides protection type information.
ARVALID: Read Address Valid Output port indicating when the read address and control signals are valid.
ARREADY: Read Address Ready. Input port that indicates when the slave is ready to accept the address and
control signals.

Read Data Channel : -

RID: Read Data ID Input port that carries the ID tag of the read data.
RDATA: Read Data Input port that carries the data being read from the slave.
RRESP: Read Response Input port that provides the response information for the read transaction.
RLAST: Read Last Input port that indicates the last transfer in a read burst.
RVALID: Read Data Valid Input port indicating when the read data is valid.
RREADY: Read Data Ready Output port that indicates when the master is ready to accept the read data.

Write Address Channel :-

AWID: Write Address ID Output port that carries the ID tag of the write address.
AWADDR: Write Address Output port that carries the address of the write transaction.
AWLEN: Burst Length Output port that defines the number of data transfers in the burst.
AWSIZE: Burst Size Output port that defines the size of each transfer in the burst.
AWBURST: Burst Type Output port that defines the burst type (fixed, incrementing, wrapping).
AWLOCK: Lock Type Output port that provides the lock status information.
AWCACHE: Cache Type Output port that carries the cache type information.
AWPROT: Protection Type Output port that provides protection type information.
AWVALID: Write Address Valid Output port indicating when the write address and control signals are valid.
AWREADY: Write Address Ready Input port that indicates when the slave is ready to accept the address and
control signals.

Write Data Channel :-

WID: Write Data ID Output port that carries the ID tag of the write data.
WDATA: Write Data Output port that carries the data being written to the slave.
WSTRB: Write Strobe Output port that indicates which byte lanes contain valid data.
WLAST: Write Last Output port that indicates the last transfer in a write burst.
WVALID: Write Data Valid Output port indicating when the write data is valid.
WREADY: Write Data Ready Input port that indicates when the slave is ready to accept the write data.
 Write Response Channel :-
BID: Write Response ID Input port that carries the ID tag of the write response.
BRESP: Write Response Input port that provides the response information for the write transaction.
BVALID: Write Response Valid Input port indicating when the write response is valid.
BREADY: Write Response Ready Output port that indicates when the master is ready to accept the write
response.

2. Explain functioning of AXI protocol?

Masters (Students): These are the devices that need to read or write data. They initiate the transactions.
Slaves (Librarians): These are the devices that provide or store the data. They respond to the requests from
the masters.
Channels of Communication
Just like a library has different desks for different services, the AXI protocol has separate channels for different
types of communication to keep things organised and efficient.
Read Address Channel (Requesting a Book):
The student goes to the "Request Desk" and gives the librarian the details about the book they want
(address).The librarian notes down the request (address and control information) and confirms when they
are ready to look for the book.
Read Data Channel (Receiving the Book):
The librarian fetches the book and hands it over to the student.The student confirms they have received the
book.If there’s a multi-volume request, the librarian keeps handing over the books one by one, and the
student confirms receipt until the last book (data burst).
Write Address Channel (Returning a Book):
● The student goes to the "Return Desk" and tells the librarian they want to return a book (write address).
● The librarian notes down the return request and confirms when they are ready to process it.
Write Data Channel (Returning the Book):
● The student hands over the book to the librarian.
● The student confirms they have given the book back.
● If returning multiple books, the student hands over each book one by one until the last book (data burst).
Write Response Channel (Acknowledgment of Return):
● After checking the returned book, the librarian gives the student a receipt (response) to confirm everything
is in order.
● The student confirms they have received the receipt.
Key Features
● Burst Mode: Like borrowing multiple volumes of a book series in one go instead of making multiple
trips.
● Data Strobes: Ensuring the student knows exactly which parts of the book are being checked in or out.

● Valid and Ready Signals: Like a green light system indicating when the student or librarian is ready for
the next step, preventing miscommunication.
Benefits
● Efficiency: Clear roles and separate channels mean everyone knows what to do and when, reducing
waiting times and errors.
● High Performance: The library can handle many requests quickly, just like AXI can support high-speed
data transfers.
 ● Flexibility: Different students can request and return books simultaneously without interfering with
each other, just like multiple masters can communicate with multiple slaves independently.

3. What is meant by AXI bus?

4. Where is the AXI protocol used?
protocol is a widely used interface standard in the field of digital electronics . It is primarily used for
communication between different components in a system - on - chip ( SoC ) design , such as processors ,
memory controllers , and peripheral devices .
One of the main applications of the AXI protocol is in the design and implementation of complex SoCs , where
multiple components need to communicate with each other efficiently . The protocol provides a standardised
way for these components to exchange data and control signals , ensuring smooth and reliable operation of
the entire system .
Moreover , the AXI protocol also offers advanced features such as burst transfers , out - of - order data delivery
, and multiple data channels , making it suitable for high - performance systems . It is also highly configurable ,
allowing designers to tailor it to their specific requirements .

5. What is a deadlock in AXI protocol?

Deadlock is a scenario where a transfer #1 cannot fully complete while transfer #2 is running. To finish, #2
requires transfer #1 to complete first, creating an endless loop that is never resolved. You can read more about
the Dining Philosophers Problem here.
From the Xilinx’s Interconnect Documentation 2, we can see how a deadlock situation can form:
Master M1 reads from Slave device S1 using ID0.
Master M1 then reads from Slave device S2 using the same ID thread ID0.
Master M2 then reads from Slave device S2 with a different ID ID1.

Master M2 then reads from Slave device S1 using the same ID thread ID1.
Slave S1 responds to Master M2 first. It is allowed to respond to M2 before M1 first, since the two Masters
have different IDs. However, the AXI Crossbar cannot pass the response to M2 because Master M2 must first
receive its response from Slave S2.
Slave S2 responds to Master M1 first without reordering. But the AXI Crossbar cannot pass the response to
Master M1 because M1 must first receive its response from Slave S1, resulting in a deadlock situation.
Helpfully, the AXI Interconnect IP already resolves this concern by mandating the “Single Slave per ID” rule,
where generally only one master device can talk to any slave at any given time. With this in-order rule, the
Read transaction in step 2 from M1 to S2 is stalled until S1 completes its response to M1. Similarly, the
transaction between M2 and S1 in step 4 is stalled until S2 completes its response to M2. This is important to
keep in mind as the AXI protocol itself has no in-order check between Read and Write transactions, meaning
that deadlock can occur elsewhere, especially when combining multiple Interconnects and SmartConnects
together.

6. What is the handshake in AXI?

All AXI channels use the same VALID/READY handshake process to transfer address, data, and control
information. This two-way flow control mechanism means both the Manager and Subordinate can control the
rate that the information moves between Manager and Subordinate. The source generates the VALID signal to
indicate when the address, data, or control information is available. The destination generates the READY
 signal to indicate that it can accept the information. Transfer occurs only when both the VALID and READY
signals areHIGH.When VALID is asserted, it must remain asserted until the handshake occurs, at a rising clock
edge when VALID and READY are both asserted.

7. What is AXI ordering?

The AXI system imposes no ordering restrictions between read and write transactions. Read and write can be
completed in any order, even if the read address AXI ID (ARID) of a read transaction is the same as the write
address AXI ID (AWID) of a write transaction. If a master requires a given relationship between a read
transaction and a write transaction, it must ensure that the earlier transaction is completed before it issues a
subsequent transaction. A master can consider the earlier transaction complete only when

For a read transaction, it receives the last of the read data.

For a write transaction, it receives the write response.

8. What are the three types of AXI protocols?

AXI3
AXI4
AXI-Lite
9. What is register slice in AXI?
When you have a register slice in AXI, it means you have divided a larger register space into smaller sections
or slices for more efficient access or organization. These slices might correspond to specific functionalities or
control registers within a peripheral or module.
For example, in a memory-mapped peripheral, you might have a register block containing multiple registers
for configuring different settings or accessing different status information. Each of these registers could be
considered a slice within the overall register space.
By organizing registers into slices, it can make the design more modular, easier to manage, and potentially
reduce access conflicts if different parts of the system need to access different registers simultaneously.
Additionally, it can help with readability and maintainability of the hardware design.

10. What is AXI fifo?

In the context of the Advanced eXtensible Interface (AXI), an AXI FIFO (First-In, First-Out) is a hardware
component designed to temporarily store data in a FIFO manner, where the data items are read out in the
same order they were written in.
AXI FIFOs are commonly used in digital designs to manage data flow between different components of a
system. They are particularly useful when there is a need to buffer data between components operating at
different speeds or with varying data arrival rates.
Data Storage: AXI FIFOs store data items in a sequential order, similar to a queue. New data is written into the
FIFO at one end, while older data is read out from the other end.
Interface: AXI FIFOs typically have AXI interfaces, allowing them to seamlessly integrate into systems that use
the AXI protocol for communication between components.
Depth: The depth of an AXI FIFO refers to the number of data items it can store. Deeper FIFOs can hold more
data but may introduce additional latency.
 Synchronisation: AXI FIFOs are often used for synchronisation purposes, ensuring that data is transferred
between components without loss or corruption, even when those components operate at different clock
speeds or have varying throughput rates.
Flow Control: Some AXI FIFO implementations support flow control mechanisms to manage data flow
dynamically, preventing overflow or underflow conditions. Flow control can involve signals such as "almost
empty" and "almost full" flags to indicate when the FIFO is close to being empty or full, respectively.

11. How many channels are in AXI protocol? Explain the operation channel detail. of each
Read Address Channel:
The Read Address channel is used by a master to initiate read transactions.
The master sends requests to read data from a specific address in the slave device's memory or register
space.It includes signals such as the read address, read data length, and read burst type.
Read Data Channel:
The Read Data channel is used by the slave to return data to the master in response to read requests.
The slave sends back the requested data along with additional information like response status.
It includes signals such as the read data, response status, and read completion indication.
Write Address Channel:
The Write Address channel is used by a master to initiate write transactions.
The master sends requests to write data to a specific address in the slave device's memory or register space.
It includes signals such as the write address, write data length, and write burst type.
Write Data Channel:
The Write Data channel is used by the master to send data to the slave as part of write transactions.
The master sends the data to be written along with other information like byte enable signals.
It includes signals such as the write data and byte enables.
Write Response Channel:
The Write Response channel is used by the slave to return response information to the master for write
transactions.The slave sends back response signals indicating the status of the write operation.
It includes signals such as the write response status and write completion indication.

12. What is AXI interrupt controller?

AXI Interrupt Controller concentrates multiple interrupt inputs from peripheral devices to a single interrupt
output to the system processor.
13. Explain the AXI response types?
Every AXI transaction includes one or more response transfers sent by the Subordinate to indicate the result of
the transaction.
Transactions on the write channels have one or more write responses.
Transactions on the read channels have one or more read responses.
OKAY - Non-exclusive write: The transaction was successful. If the transaction includes write data, the
updated value is observable.
Exclusive write: Failed to update the location.
EXOKAY - Exclusive writing succeeded. This response is only permitted for an exclusive write.
SLVERR - The request has reached an end point but has not completed successfully. The location might not be
fully updated. Typically used when there is a problem within a Subordinate such as trying to access a read-only
or powered-down function.
 DECERR - The request has not reached a point where data can be written. The location might not be fully
updated. Typically used when the address decodes to an invalid address.
DEFER - Write was unsuccessful because it cannot be serviced at this time. The location is not updated. This
response is only permitted for a WriteDeferrable transaction.
TRANSFAULT - Write was terminated because of a translation fault which might be resolved by a PRI request.
UNSUPPORTED - Write was unsuccessful because the transaction type is not supported by the target. The
location is not updated. This response is only permitted for a WriteDeferrable transaction.

14. What is fixed burst type?

This Burst type is used for repeated accesses to the same location such as when loading or emptying a FIFO.
• The address is the same for every transfer in the burst.
• The byte lanes that are valid are constant for all transfers. However, within those byte lanes, the actual bytes
that have WSTRB asserted can differ for each transfer.
• The Length of the burst can be up to 16 transfers.
• The FIXED burst type can only be used with WriteNoSnoop or ReadNoSnoop Opcodes. See

15. Explain the concept of AXI 4KB boundary condition?

The concept of the 4KB boundary condition in the AXI protocol refers to the constraint that an AXI
transaction should not cross a 4KB address boundary. This is an important aspect to consider when designing
systems that use the AXI protocol for data transfers.
The primary reason for the 4KB boundary condition is to simplify address decoding and to maintain
compatibility with memory management schemes.
Memory Management: Many memory management units and page tables use 4KB pages. Ensuring that AXI
transactions do not cross these boundaries simplifies the interaction with these units.
Address Decoding: Simplifying address decoding within the interconnect and memory controllers can be
achieved by enforcing this boundary condition.
Transaction Management: Handling transactions that span across different memory regions or devices can
be complex and error-prone. The 4KB boundary condition helps avoid these complexities.
When designing AXI-based systems, transactions that might cross a 4KB boundary need to be split into
multiple transactions.
Burst Transactions: In AXI, burst transactions are sequences of transfers with a defined pattern. If a burst
transaction starts within a 4KB page but extends beyond its boundary, it must be split into two separate
bursts.
Address Calculation: The master device initiating the transaction must calculate the address and length of
the burst to ensure it does not cross the 4KB boundary. If a burst would cross the boundary, it needs to
terminate at the boundary and start a new burst at the beginning of the next 4KB page.
Interconnect Handling: AXI interconnects and memory controllers need to handle transactions properly and
often enforce this boundary condition, ensuring data integrity and system stability.

16. Difference between AXI3 and AXI4?

AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to 256 beats. AXI3
supports write interleaving. AXI4 does NOT support write interleaving AXI3 supports locked transfers, AXI4
does NOT support locked transfers AXI4 supports QoS, AXI3 does NOT suppor QoS.

17. What is the difference between AHB and AXI protocol?

AXI is more complex and offers higher performance compared to AHB. AXI supports out-of-order
transaction execution, burst transactions, and other advanced features, making it suitable for
high-performance systems. AHB is simpler and more straightforward, making it suitable for simpler systems or
those with less demanding performance requirements.
AXI includes additional features such as burst transfers, burst lengths, out-of-order transaction support,
multiple outstanding transactions, and more advanced pipelining compared to AHB.
AHB is an older protocol, while AXI is more recent and backward compatible with AHB. This means that AXI
can interoperate with AHB peripherals and vice versa, allowing for smoother transitions between different
generations of ARM-based systems.
AXI is designed to be more scalable than AHB, making it suitable for a wider range of system configurations,
from simple embedded systems to complex multi-core processors.
AXI incorporates features to improve signal integrity and reduce power consumption compared to AHB