Study Plan (DLD)
Study Plan (DLD)
Day 1: Fundamentals
2. Number Systems
o DE Morgan’s Theorems.
1. Boolean Functions
2. Logic Gates
3. Tabulation Method
3. Code Converters
o BCD adder.
2. Magnitude Comparators
o Priority encoders.
1. ROM
o Types of ROM.
2. Flip-Flops
1. Memory Units
3. Lab Assignments
o Simulate designs using Verilog HDL/VHDL.
Notes:
• Allocate 4-6 hours daily to cover the topics and solve related problems.
• Use tools like Verilog/VHDL simulators and MultiSum for practical understanding.