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Digital Lab1

The document outlines various digital logic experiments, including the realization of logic gates, half adders, full adders, multiplexers, and different types of counters (Johnson, ring, decade, and up/down). Each experiment is presented with Verilog code for the modules and corresponding test benches to simulate their behavior. The structure demonstrates the implementation and testing of fundamental digital circuits using hardware description language.

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sreyadelna
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11 views11 pages

Digital Lab1

The document outlines various digital logic experiments, including the realization of logic gates, half adders, full adders, multiplexers, and different types of counters (Johnson, ring, decade, and up/down). Each experiment is presented with Verilog code for the modules and corresponding test benches to simulate their behavior. The structure demonstrates the implementation and testing of fundamental digital circuits using hardware description language.

Uploaded by

sreyadelna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXPERIMENT 1- REALIZATION OF LOGIC GATES

module gate(
input a,
input b,
output ANDgate,
output ORgate,
output NANDgate,
output NORgate,
output XORgate
);
and a1(ANDgate,a,b);
or o(ORgate,a,b);
nand na1(NANDgate,a,b);
nor n1(NORgate,a,b);
xor x1(XORgate,a,b);
endmodule

module gate1(
input a,
input b,
output ANDgate,
output ORgate,
output NANDgate,
output NORgate,
output XORgate
);
assign ANDgate=a&b;
assign ORgate=a|b;
assign NANDgate=~(a&b);
assign NORgate=~(a|b);
assign XORgate=a^b;
endmodule

module gate2(
input a,
input b,
output reg ANDgate,
output reg ORgate,
output reg NANDgate,
output reg NORgate,
output reg XORgate
);
always @(*) begin
ANDgate = a & b; ORgate = a | b;
NANDgate = ~(a & b);
NORgate = ~(a | b);
XORgate = a ^ b;
end
endmodule
module gates_tb(
);
reg a,b;
wire ANDgate,ORgate,NANDgate,NORgate,XORgate;
gates g1(a,b,ANDgate,ORgate,NANDgate,NORgate,XORgate);
initial
begin
a=1'b0;
b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10 $finish;
end
endmodule

module boolean_simplify(
input a,
input b,
input c,
output y
);
assign y=(~b)|(~c);
endmodule
module boolean_tb(
);
reg a,b,c;
wire y;
boolean_simplify b1(a,b,c,y);
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10 $finish;
end
endmodule

EXPERIMENt_2 - HALFADDER
module halfadder(
input a,
input b,
output s,
output c
);
reg s,c;
always @(a or b)
begin
{c,s}=a+b;
end
endmodule
module halfadder1(
input a,
input b,
output s,
output c
);
assign s=a^b;
assign c=a&b;
endmodule

module halfadder2(
input a,
input b,
output s,
output c
);
xor x1(s,a,b);
and a1(c,a,b);
endmodule

module halfadder_tb(
);
reg a,b;
wire s,c;
halfadder h1(a,b,s,c);
initial
begin
a=1'b0;
b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10 $finish;
end
endmodule
EXPERIMENT_2 FULLADDER
module fulladder(
input a,
input b,
input c,
output s,
output cout
);
wire c1,c2,s1;
halfadder h1(a,b,s1,c1);
halfadder h2(s1,c,s,c2);
or o1(cout,c1,c2);
endmodule

module fulladder_tb(
);
reg a,b,c;
wire s,cout;
fulladder f1(a,b,c,s,cout);
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10 $finish;
end
endmodule
EXPERIMENT_3 - MUX
module mux4to1(
input [3:0] d,
input [1:0] s,
output reg y
);
always @ (s or d)
begin
case(s)
2'b00:y=d[3];
2'b01:y=d[2];
2'b10:y=d[1];
2'b11:y=d[0];
endcase
end
endmodule

module mux_tb(
);
reg [3:0] d;
reg [1:0] s;
wire y;
mux4to1 m1(d,s,y);
initial
begin
s=2'b00;d=4'b0000;
#10 s=2'b01;d=4'b0001;
#10 s=2'b10;d=4'b0010;
#10 s=2'b11;d=4'b0101;
#10 $finish;
end
endmodule
EXPERIMENT_4-JHONSON COUNTER
module jhonsoncounter(
input clk,
input clr,
output [3:0] Q
);
reg [3:0] Q;
always @(posedge clk or clr)
begin
if(!clr)
Q=4'b0000;
else
begin
Q[3]<=~Q[0];
Q[2]<=Q[3];
Q[1]<=Q[2];
Q[0]<=Q[1];
end
end
endmodule

module jhonson_tb(
);
reg clk,clr;
wire [3:0] Q;
jhonsoncounter j1(clk,clr,Q);
initial
begin
clr=1'b0;
#10 clr=1'b1;
clk=0;
#80 $finish;
end
always #5 clk=~clk;
endmodule
EXPERIMENT_4 RING COUNTER
module ringcounter(
input clr,
input clk,
output [3:0] Q
);
reg [3:0] Q;
always @(posedge clk or clr)
begin
if(!clr)
Q=4'b1000;
else
begin
Q[3]<=Q[0];
Q[2]<=Q[3];
Q[1]<=Q[2];
Q[0]<=Q[1];
end
end
endmodule

module ring_tb(
);
reg clk,clr;
wire [3:0] Q;
ringcounter r1(clr,clk,Q);
initial
begin
clr=1'b0;
#10 clr=1'b1;
clk=0;
#50 $finish;
end
always #5 clk=~clk;
endmodule
EXPERIMENT_5- DECADE COUNTER
module decade(
input clk,
input clr,
output [3:0] Q
);
reg [3:0] Q;
always @(posedge clk or clr)
begin
if(!clr)
Q=4'b0000;
else if(Q==4'b1001)
Q=4'b000;
else
Q=Q+1;
end
endmodule

module decade_tb(
);
reg clk,clr;
wire [3:0] Q;
decade dc1(clk,clr,Q);
initial
begin
clr=1'b0;
#10 clr=1'b1;
clk=0;
#100 $finish;
end
always #5 clk=~clk;
endmodule
EXPERIMENT_5 UPDOWN COUNTER
module up_down(
input mode,
input clk,
input clr,
output [2:0] Q
);
reg [2:0] Q;
always @(posedge clk or clr)
begin
if(!clr )
Q=3'b000;
else if(mode==0)
Q=Q+1;
else if(mode==1)
Q=Q-1;
end
endmodule

module upcounter_tb(
);
reg clk,clr,mode;
wire [2:0] Q;
up_down c1(mode,clk,clr,Q);
initial
begin
clr=1'b0;
mode=1'b0;
#10 clr=1'b1;
clk=0;
#70
mode=1'b1;
#70
$finish;
end
always #5 clk=~clk;
endmodule

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