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Instruction Formats of 8086

The document outlines the instruction formats of the 8086 microprocessor, detailing the structure of instructions, including opcode, data size bits, and operand fields. It provides examples of various instructions, illustrating how to encode them into machine code, including the use of register and memory addressing modes. Additionally, it explains the significance of bits such as D and W in determining operand roles and data sizes in instructions.

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Navya Shree J
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11 views6 pages

Instruction Formats of 8086

The document outlines the instruction formats of the 8086 microprocessor, detailing the structure of instructions, including opcode, data size bits, and operand fields. It provides examples of various instructions, illustrating how to encode them into machine code, including the use of register and memory addressing modes. Additionally, it explains the significance of bits such as D and W in determining operand roles and data sizes in instructions.

Uploaded by

Navya Shree J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Instruction Formats of 8086

The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes
and it defines the operation to be carried out by the instruction.
Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2
is the source or destination operand.

D=1 Specifies that the register operand is the destination operand.


D=0 indicates that the register is a source operand.
Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data
W=0 indicates 8 bit operation
W=1 indicates 16 bit operation

The second byte of the instruction usually identifies whether one of the operands is in
memory or whether both are registers.
This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and
the Register/Memory (R/M) field.
Register field occupies 3 bits. It defines the register for the first operand which is specified
as source or destination by the D bit.

The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second
operand as shown below.
MOD 11
Effective Address Calculation

In the above, encoding of the R/M field depends on how the mode field is set. If
MOD=11 (register to register mode), this R/M identifies the second register operand.
MOD selects memory mode, then R/M indicates how the effective address of the memory
operand is to be calculated. Bytes 3 through 6 of an instruction are optional fields that
normally contain the displacement value of a memory operand and / or the actual value
of an immediate constant operand.

Example 1 : MOV CH, BL


This instruction transfers 8 bit content of BL into CH
The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by
the REG field of byte 2 is a source or destination operand.
D=0 indicates BL is a source operand.
W=0 byte operation
In byte 2, since the second operand is a register MOD field is 112.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV CH, BL is
10001000 11 011 101
Byte 1 Byte 2 = 88DD16
Example 2 : SUB Bx, (DI)
This instruction subtracts the 16 bit content of memory location addressed by DI and DS
from Bx. The 6 bit Opcode for SUB is 0010102.
D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit
operation.
MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101
2 B 1 D
2B1D16

Example 3 : Code for MOV 1234 (BP), DX


Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source
register. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate it is
a word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and a
displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.

Example 4 : Code for MOV DS : 2345 [BP], DX


Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source
register. The REG field must be 010 to indicate DX register. The w bit must be 1 to indicate it is
a word operation. 2345 [BP] is specified with MOD=10 and R/M =110 and displacement = 2345
H.

Whenever BP is used to generate the Effective Address (EA), the default segment would be SS.
In this example, we want the segment register to be DS, we have to provide the segment override
prefix byte (SOP byte) to start with. The SOP byte is 001 SR 110,where SR value is provided as
per table shown below.

To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte
code for this instruction would be 3E 89 96 45 23 H.

Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without
SOP byte, as SS is already the default segment register in this case.

Example 5 :
Give the instruction template and generate code for the instruction
ADD OFABE [BX] [DI], DX (code for ADD instruction is 000000)

ADD OFABE [BX] [DI], DX


Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the source
register. The REG field must be 010 to indicate DX register. The w must be 1 to indicate it is a
word operation. FABE (BX + DI) is specified using MOD value of 10 and R/M value of 001 (from
the summary table). The 4 byte code for this instruction would be
Example 6 :
Give the instruction template and generate the code for the instruction MOV AX, [BX]
(Code for MOV instruction is 100010)
AX destination register with D=1 and code for AX is 000 [BX] is specified using 00 Mode and
R/M value 111

It is a word operation

Questions:
1. Give the instruction template and generate the code for the instruction
MOV AX,[BX].

2. Give the instruction template and generate code for the instruction
ADD OFABE [BX] [DI], DX (code for ADD instruction is 000 000)

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