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SC2151A Type-C/ PD and DPDM Fast Charge Controller with

CC/CV Internal Feedback Compensation Integrated
1 Descriptions
SC2151A is a Type-C / PD and DPDM fast charge controller, with internal feedback compensation integrated. It complies with
the latest Type-C and PD 3.0 standards supports the most popular high voltage fast charge protocols with DPDM interface. It
targets for the wall adapters and power strips applications.

SC2151A minimizes external components by integrating USB PD baseband PHY, Type-C detection, VBUS discharging path,
VCONN supply, programmable feedback compensation, voltage and current sense, 10bit high performance ADC, dual 10bit
DACs, NMOS gate driver, I2C interface and protection circuits. It is embedded 32-bit high performance micro-controller with
24K-Bytes OTP and 2K-Byte RAM, which provides cost effective solutions to many applications.

SC2151A supports various protection mechanisms including over voltage protection, under voltage protection, over current
protection, short circuit protection, over temperature protection, DPDM over voltage protection, CC over voltage protection,
VCONN over voltage, over current and short protection, so to effectively ensure stable and reliable operation of system.

2 Features
• USB Type-C • MCU Subsystem
➢ Support Type-C DFP protocols ➢ Integrated 32bit high performance MCU core
➢ Configurable resistors RP ➢ 24-KB OTP and 2-KB RAM
➢ Support I2C interface and multiple I/Os
• USB Power Delivery
➢ Support sleep mode, min IQ <=100uA
➢ Support DFP / UFP / DRP USB PD 3.0
➢ Hardware BMC transmitter and receiver • Analog Block
➢ Full feature physical layer ➢ Dual DACs for voltage regulation
➢ Hardware CRC ➢ 10-bit ADC to monitor the voltage / current / other
➢ Hardware reset signals
➢ Integrate PD 3.0 protocol engine ➢ Integrated current sense amplifier
➢ Integrate VCONN and support SOP’ for e-marker ➢ Integrated NMOS gate driver
➢ Integrated VBUS discharging paths at both sides of
• DPDM Fast Charging Interface
isolation MOS
➢ Integrate firmware controlled DPDM interface
➢ Integrated temperature sense module
➢ Support Apple charging, BC1.2, DCP, HVDCP, FC,
o Protections
AFC, FCP, SCP, VOOC, UART, I2C and other
➢ On chip OVP, DPDM OVP, CC OVP
proprietary charging protocols
➢ VBUS to CC / DPDM short protection
• Power
➢ GND to CC / DPDM short protection
➢ Wide operation range: 3.3V to 22V (26V tolerant)
o Package
➢ Integrate programmable feedback compensation.
➢ 16-pin QFN, 4mm x 4mm x 0.75mm

3 Applications 4 Device Information

• Wall adapters ORDER NUMBER PACKAGE BODY SIZE
• Power strips SC2151A 16 pin QFN 4mm x 4mm x 0.75mm

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5 Typical Application Circuit

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6 Terminal Configuration and Functions

TOP VIEW of SC2151A

TERMINAL
I/O DESCRIPTION
NUMBER NAME

ADC0 I ADC input channel0

NTC I/O Remote thermal sensor connection node for board temperature monitoring.

1 GPIO0 I/O General purpose input and output port 1.

JTAG_TMS I/O JTAG data line.

UART_RX I Universal Asynchronous Receiver/Transmitter, input port.

2 NDRV O N-MOS driver. Connect this pin to the gate of load switch.

3 LV I/O Internal LDO output. Connect a 1uF ceramic capacitor between this pin and ground.

4 DP I/O USB DP line of the fast charging interface.

5 DM I/O USB DM line of the fast charging interface.

Type-C connector configuration channel 1, used to detect a device plug event, determine the
6 CC1 I/O cable orientation, transmit or receive PD protocols and configured as the output of VCONN
supply.

Type-C connector configuration channel 2, used to detect a device plug event, determine the
7 CC2 I/O cable orientation, transmit or receive PD protocols and configured as the output of VCONN
supply.

8 CS+ I Positive input of current sense amplifier.

9 CS- I Negative input of current sense amplifier.

SDA I/O I2C interface data line.

10
GPIO2 I/O General purpose input and output port 2.

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JTAG_TMS I/O JTAG data line.

SCL I/O I2C interface clock line.

GPIO3 I/O General purpose input and output port 2.

11
JTAG_CLK I JTAG clock line.

UART_TX O Output port of universal asynchronous receiver/transmitter module.

SCL I/O I2C interface clock line.

ADC4 I ADC input channel4

12
NTC I/O Remote thermal sensor connection node for board temperature monitoring.

GPIO4 I/O General purpose input and output port 2.

Connected to the VBUS line of the USB Type-C port. It is also used to sense the VBUS voltage
13 VBUS_MON I
of the port and is internally connected to the discharge path.

14 OPTO I/O Current sink output for optocoupler connection.

Power supply pin of this IC which should be connected to VBUS power node. It is also used to
15 VBUS_PWR I sense the VBUS voltage and is internally connected to the discharge path. It is recommended
to connect at least 1µF bypass capacitor from this pin to ground close to the IC.

16 GND I/O Ground of IC.

17 Thermal Pad - Connect pad to GND.

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7 Electrical Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)

Symbol Description Min. Max. Unit

VBUS_PWR, VBUS_MON -0.3 26 V

DP, DM -0.3 12 V

Voltage (2) IO0, SDA/IO2, SCL/IO3, NTC/GPIO4 -0.3 5.5 V

Operating junction temperature -40 150 °C

Storage temperature -65 150 °C

TL Lead Temperature 260 °C

TD Continuous power dissipation (TA=25°C) 1.25 W

TΘJA (3) Junction to ambient thermal resistance 100 °C/W

TΘJC (3) Junction to case thermal resistance 12 °C/W

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
(2) All voltages are with respect to network ground terminal.
(3) Measured on JESD51-7, 4-layer PCB.

7.2 ESD Ratings

Symbol Description Min. Max. Unit

Human-body Model (HBM) (2) All pins -2 2 kV

VESD (1)
(3)
Charged-device Model (CDM) -750 750 V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.

7.3 Recommended Operation Conditions

Symbol Description Min. Typ. Max. Unit

VBUS _PWR VBUS_ PWR operation voltage 3.3 22 V

CVBUS_PWR Bulk capacitor at VBUS_PWR pin 300 1600 µF

TA Operating ambient temperature -40 85 C

TJ Operating junction temperature -40 125 C

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7.4 Electrical Characteristics

TJ= 25°C and VBUS = 5V, VBAT = 3.6V unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VBUS_PWR Pin)
VBUS_PWR VBUS_PWR supply range 3.3 22 V
VBUS_PWR under voltage lockout
3.2 3.3 V
VBUS_PWR_UVLO threshold
Hysteresis 200 mV
Quiescent current during active VBUS_PWR=8V, all module is
IQACT 10 mA
mode active

VBUS_PWR=5V, standby mode，

Quiescent current during standby
IQSBY1 (DPDM wake up), all analog 0.3 1 mA
mode1
peripherals is enabled.

Control loop disable ， MCU and

Quiescent current during standby
IQSBY2 peripherals all disabled except CC 100 µA
mode2
and DPDM.

IDIS_VBUS_PWR Discharging current at VBUS_PWR Register-Programmable 120 mA

110
115
VBUS_PWR_OVP VBUS_PWR OVP Register-Programmable %
120
Disable

4 µs
VBUS_PWR over-voltage debounce
TVBUS_PWR_OVP Register-Programmable
time
40 µs

4 µs
TDPDM_OVP DPDM over-voltage debounce time Register-Programmable
40 µs

75
VBUS_PWR_UVP VBUS_PWR UVP Register-Programmable 85 %
95

20 µs
VBUS_PWR under-voltage
TVBUS_PWR_UVP Register-Programmable
debounce time
40 µs

VBUS_MON short circuit protection Register-Programmable (default: 2.75 V

VMON_SCP_TH
threshold. 3.2V) 3.2 V
NMOS GATE DRIVER

VGATE-VBUS_MON，
VDRV Driving voltage 5 V
VBUS_PWR = 3.3V
VCLAMP_GS Driver clamp voltage 7 V
ADC
VADC_REF Reference voltage for ADC 2.248 V
NADC Resolution 10 Bits
RSAMPLE ADC sample rate 50 Ksps

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Ratio from VBUS_PWR voltage

KADC_CH0 Trimming option 1/10
sense
Ratio from VBUS_MON voltage
KADC_CH1 Trimming option 1/10
sense
KADC_CH3 Ratio from DP/DM 1/3
KADC_CH4 Ratio from ADC0 voltage sense 1
KADC_CH5 Ratio from ADC4 voltage sense 1
Ratio from Internal temperature
KADC_CH6 1
sense
Range 3 22 V
LSB 21.95 mV
ADCVBUS_PWR
3.3V, 5V, 9V -100 100 mV
Error
12V, 15V, 20V -200 200 mV
Range 0 5.27 V
ADCDP,
LSB 65.86 mV
ADCDM
Error Full Range -150 150 mV
Range 0 2.248 V
ADCGPIO LSB 2.195 mV
Error -5 5 mV
INL Integral non-linearity -1.0 1.0 LSB
DNL Differential non-linearity -0.5 0.5 LSB
CURRENT SENSE
Ratio from current sense to
KI1 20
ADC/comparators
Ratio from current sense to
KI2 40
ADC/comparators
VOCP OCP threshold 45 mV
VOCP_DT OCP debounce time 20 ms
VCS_OFFSET Zero offset voltage 200 mV

VDD < 5V, VCS < VCS_ACOFF when

VDD discharge is on
VCS_ACOFF AC-off trigger 0.5 mV
100Ma*5mOhm*40 =0.5Mv
0.5Mv*40=20Mv0215
TYPE-C/PD PROTOCOLS
VBUS_PWR=3.3V,
ICC_80Ua CC1/2 pull up current 64 80 96 mA
CSRC_I = 00b

VBUS_PWR=3.3V,
ICC_180Ua CC1/2 pull up current 165.6 180 194.4 mA
CSRC_I = 01b

VBUS_PWR=3.3V,
ICC_330Ua CC1/2 pull up current 303.6 330 356.4 mA
CSRC_I = 10b

RCC_open CC1/2 open impedance CC1/2 in disable status 126 kΩ

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VCC_0P2_th_src CC1/2 0.2V comparison threshold CC1/2 as source 0.15 0.2 0.25 V

VCC_0P4_th_src CC1/2 0.4V comparison threshold CC1/2 as source 0.35 0.4 0.45 V

VCC_0P66_th_src CC1/2 0.66V comparison threshold CC1/2 as source 0.61 0.66 0.7 V

VCC_0P8_th_src CC1/2 0.8V comparison threshold CC1/2 as source 0.75 0.8 0.85 V

VCC_1P23_th_src CC1/2 1.23V comparison threshold CC1/2 as source 1.18 1.23 1.28 V

VCC_1P6_th_src CC1/2 1.6V comparison threshold CC1/2 as source 1.5 1.6 1.65 V

VCC_2P6_th_src CC1/2 2.6V comparison threshold CC1/2 as source 2.45 2.6 2.75 V

Comparison threshold at CC1/CC2 CCx OVP detection

VTH_6.15V 5.9 6.15 6.4 V
pin
Source output impedance at
the Nyquist frequency of [USB

ZDriver PD data Tx output impedance 2.0] low speed (750 kHz) 33 75 Ω

while the source is driving the
CC line.

High level voltage Swing for CC PD

VSwing 1.05 1.125 1.2 V
data

Capacitance on CC1/CC2 pin

TCC_RISING PD data rising time 300 ns
<600Pf

Time to cease driving the line

TEndDriveBMC after the end of the last bit of 23 ms
the Frame.
Time to cease driving the line
THoldLowBMC after the final high-to-low 1 mA
transition.
VBUS_PWR=3.3V,
ICC_80Ua CC1/2 pull up current 64 80 96 mA
CSRC_I = 00b

VCONN SWITCH

VVCONN VCONN input voltage 3 5.5 V

RVCONN VCONN switch on resistance VDD5V=3.3V 40 Ω

IVCONN VCONN current capability 35 mA

PROTOCOL INTERFACES（DP and DM Pins）

RSHORT DP DM short resistance VBUS_PWR = 5V 40 Ω

V3.3V DPDM 3.3V buffer output voltage VBUS_PWR = 5V 3.2 3.3 3.4 V
V2.7V DPDM 2.7V buffer output voltage VBUS_PWR = 5V 2.6 2.7 2.8 V
V1.96V DPDM 1.96V buffer output voltage VBUS_PWR = 5V 1.9 2 2.1 V
VTH3V comparator threshold at
VTH_3V VBUS_PWR = 5V 2.9 3 3.1 V
DPDM pin
VTH2.2V comparator threshold at
VTH_2.2V VBUS_PWR = 3.3V 2.1 2.2 2.3 V
DPDM pin

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VTH1.35V comparator threshold at

VTH_1.35V VBUS_PWR = 3.3V 1.25 1.35 1.45 V
DPDM pin
VTH0.425V comparator threshold at
VTH_0.425V VBUS_PWR = 3.3V 0.35 0.425 0.5 V
DPDM pin
VTH0.325V comparator threshold at
VTH_0.325V VBUS_PWR = 3.3V 0.25 0.325 0.4 V
DPDM pin
Output resistance of DP or DM
ROUT_30k 24 30 36 kΩ
buffer
0.6V current capability, sink/BC1.2,
IOUT_0P6V 250 uA
DP/DM
RDP/DM_DWN DP/DM pull down resistance source/HVDCP, DM 16 20 24 kΩ
RDP/DM_LKG DP/DM leakage 300 500 800 kΩ
DP/DM data ouput high voltage, Slave data output high,
VDATA_HIGH_3.3 3 3.3 3.6 V
Data_high_sel = 0b VBUS_MON = 5V

VDATA_LOW DP/DM data ouput high voltage SCP output low logic 0.2 V
IOH_DM_3P3V 3.3V current capability, DM 5 mA
000b 0.7 0.8 0.86 V
001b 1.1 1.2 1.3 V
010b 1.3 1.4 1.5 V
011b 1.7 1.8 1.9 V
VIH_TH DPDM input data rising threshold
100b 1.8 1.9 2.0 V
101b 2.0 2.1 2.2 V
110b 2.2 2.3 2.4 V
111b 2.4 2.5 2.6 V
000b 0.5 0.6 0.7 V
001b 0.9 1 1.1 V
010b 1 1.1 1.2 V
011b 1.4 1.5 1.6 V
VIL_TH DPDM input data falling threshold
100b 1.7 1.8 1.9 V
101b 1.8 1.9 2.0 V
110b 2.1 2.2 2.3 V
111b 2.2 2.3 2.4 V
VTH_OV Comparison threshold at DP/DM pin Source/DPDM OVP/SCP detection 4.5 4.75 5 V
TDATA_RISING Data output from low to high 0.3 1 μs
TDATA_FALLING Data output from high to low 0.3 1 μs
TUI Unit interval time 144 160 176 μs
Adapter transmit slave ping duration
TPING_ST 2304 2560 2816 μs
time
Adapter receive master ping
TPING_SR 2304 2560 2816 ms
duration
TPSR/TPST Ping received and transmit ratio 99 100 101 %
Terminal request bus window after
TMREQ 1 2 UI
slave ping

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Adapter request bus window after

3 5 UI
slave ping
TSREQ
Adapter request bus window after
2 5 UI
master ping
tAD Terminal attach deglitch 450 500 550 μs
00b 0.475 0.5 0.525 ms
01b 0.95 1 1.05 ms
tDD Terminal detach deglitch
10b 1.9 2 2.1 ms
11b 3.8 4 4.2 ms
THERMAL SENSOR (NTC)
VNTC NTC open loop voltage In NTC mode 2.248 V
00b 100

External NTC temperature detection 01b 20

INTC uA
bias current 10b 4
11b Disable
TDIE Internal temperature sensor range -20 105 °C
TERR Thermal Sensor Error -10 10 °C
SYSTEM CLOCK
fHF_OSC High frequence OSC 24 MHz
fLF_OSC Low frequence OSC 500 kHz

GPIO PINS（GPIO Pin）

VBUS_PWR = 3.2V ~ 21V,

VIH_GPIO Input voltage high threshold 0.7 V
measured as VIO
VBUS_PWR = 3.2V ~ 21V,
VIL_GPIO Input voltage low threshold 0.3 V
measured as VIO
VBUS_PWR = 6V, apply 4mA sink
VOH_GPIO Output voltage high threshold current from IO pin to GND 4.5 V
externally
VBUS_PWR = 6V, apply 10mA
VOL_GPIO Output voltage low threshold source current from VDD_5V to IO 0.5 V
pin externally
VPU Pull up resistor value at GPIO pin VBUS_PWR = 3.2V ~ 21V 5.6 kΩ
VPD Pull down resistor value at GPIO pin VBUS_PWR = 3.2V ~ 21V 5.6 kΩ

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8 Detailed Description 100 IO4

101 1/3 x DP/DM

8.1 Power Supply
VBUS_PWR is the power supply input pin of SC2151A. The 8.5 External Temperature Sense
operation range is from 3.3V to 22V.
SC2151A provide two port to support external temperature
For application, VBUS_MON should be connected to the sense. As shown in the figure, NTC pin source a current on
VBUS on USB port. And VBUS_PWR should be connected the RNTC, and the voltage could be sampled by 10-bit ADC.
to internal VBUS node. Source current could be configured as 100uA, 20uA or 4uA.
The over-temperature protection will be triggered if the
8.2 NMOS Gate Driver voltage is below an over-temperature protection threshold
The Type-C and USB PD specifications require the VBUS for a programmed time delay.
isolation implementation for the Type-C port. And for some
USB-A port fast charge application, VBUS isolation is 2.248V

required. SC2151A provides NMOS gate drive to control the

Source current set control
isolation MOSFET between the internal VBUS node and the
Type-C port.

The gate drivers are controlled by register bits. The voltage MCU 10bit ADC
VGS is clamp to 7V. The IC provides 4 different pull-up
RNTC
capabilities from 80kΩ to 300kΩ, and 2 pull-down
capabilities at 2kΩ or 15kΩ, so to suit different MOSFETs.

8.3 VBUS Discharging Paths

The IC integrates two VBUS discharging paths from
VBUS_MON and VBUS_PWR pins to ground respectively.
8.6 DPDM Interface
The two paths help drain the residual charge on the bulk
capacitors to meet the application requirements. The typical The SC2151A integrates DPDM interface which could be
equivalent impedance of discharge path on VBUS_MON pin configured as discharging out port (provider); The DPDM
is 1kΩ. Discharging path on VBUS_PWR pin is a constant interfaces is available for USB-A port applications. It
current from 45mA to 125mA, which could be configured by supports Apple-2.4A, BC1.2 DCP, HVDCP, FCP, SCP,
register. The discharging paths are turned on/off through VOOC and other mainstream fast charging protocols.
register settings.
8.7 Protections
8.4 ADC
8.7.1 Over-Voltage and Under-Voltage Protection
In the Type-C, USB PD or other quick charge applications,
The SC2151A monitors the VBUS voltage in real time. Once
it is necessary to monitor the VBUS voltage and current. The
the voltage exceeds the OVP threshold and the state
SC2011D integrates a 10-bit successive approximation
sustains for a programmed time, the OVP flag is set and
Analog to Digital Converter (SAR ADC) with a reference
interrupt is generated automatically. It also monitors VBUS
voltage of 2.248V at a sampling rate of 50kHz.
voltage for under-voltage protection (UVP). When VBUS
The ADC supports five-channel input as below. For voltage drops below UVP threshold and the state sustains
VBUS_MON and VBUS_PWR, an internal ratio of 1/10 is for a programmed time, the UVP flag is set and an interrupt
built in. And the ratio of DPDM channel is 1/3. is generated.

Table 1. ADC input channel The OVP threshold, UVP threshold and the detection
deglitch time can be configured through registers. The OVP
ADC_CH
Input Signal Note threshold could be configured as 110%, 115% and 120% of
_SEL[2:0]
the setting voltage. The deglitch time could be configured as
000 1/10 x VBUS_PWR with 1/10 internal divider
4µs and 40µs.
001 1/10 x VBUS_MON with 1/10 internal divider

011 IO0

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8.7.2 Protection for DPDM 8.8.4 Interrupts

The IC supports over-voltage protection of the DP/DM pin. The IC supports various interrupts, including Timer0
Once it detects any of the DP and DM voltage exceeding interrupt, ADC interrupt, I2C interrupts, DPDM interrupts,
4.8V, the IC will report the over-voltage status. analog interrupts, WDT interrupt, IOx interrupt.

8.8 MCU Controller 8.8.5 Timer

The SC2151A integrates one general timer. The clock
8.8.1 Clock source could be configured as 24Mhz high frequency
The SC2151A integrates a 24MHz high frequency clock and oscillator or 500kHz low frequency oscillator.
a 500kHz low frequency clock. Under normal working
The timer is a count-up counter, counting cycle and clock
condition, high frequency and low frequency clocks work
could be configured by registers. Overflow flag will be set
simultaneously. When in sleep mode, only the 500kHz clock
and interrupt will be generated once timer0 counts to the
works to reduce the power consumption.
end of cycle.

8.8.6 UART
8.8.2 Modes
UART can support Tx function and Rx function.
The SC2151A supports two operating modes: active mode
and sleep mode. Under active mode, each function module 8.8.7 I2C
operates normally. When in sleep mode, only the 500kHz
The SC2011D has one I2C master interface (I2C_M) and
low frequency clock, all other functions are turned off. The
one slave interface (I2C_S). The I2C slave address is
quiescent current can be as low as 100 µA in sleep mode.
(0x80/0x81).
After entering sleep mode, the system can be awakened by
interruptions, including GPIO interrupts, DPDM interrupts, 8.8.8 Watchdog
watchdog interrupts, and the timer interrupts of the 500kHz
The watchdog is a 16bit counter with 1000Hz clock source.
clock source.
When the watchdog is enabled, the watchdog counter starts
with the value of register WDT_CNT and counts up. The
8.8.3 GPIO
control register WDT_CTRL can be used to select whether
GPIO has input/output direction settings, internal pull- an interrupt or reset signal, or both occurs when the counter
up/pull-down resistor settings, and interrupt edge settings. overflows (counting to WDT_INIT).
Please see register map for details.
8.8.9 Programming
The SC2151A could be programmed through I2C interface.

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