HDL(Hardware Description

Language)
Assignment-1

1. Write the complete syntax of a Verilog design source code and testbench
code. Clearly explain the structure and purpose of each component in the
code.

module id;//Creating a module in C to write our id

initial begin//This is a procedural block,which is required to run procedural

statements

$display("Nidal");//displays my id

$display("CS24B1039");

end//procedural block end

endmodule//module's end

//modules provide encapsulation just like in OOP in c++

//We require this because we don’t have a "Global Space" like we do have in
other languages

//Taking an example of Half-Adder

module Half_Adder(input a,b,output s,cout);//A new module of inputs

a,b,s,cout

assign s=a^b;//Sum behaves like XOR Operation between both

assign cout=a&b;//And operator

endmodule//module ends here

//Testbench Code to test the above code

module test;//Module starts here

reg a,b;//registers -flip flops to store variables that alternates

wire s,cout;//wires just carry info

Half_Adder add(a,b,s,cout);//Creates a copy of Half_Adder named add

//This is used and is based on user how much copies are necessary

initial begin//procedural block begins

$monitor("At time %0t: a=%b,b=%b,s=%b,cout=%b",$time,a,b,s,cout);//Unlike

display function it monitors the change of variables

//display only prints the parameters one time while monitor does it
whenever a change is occurred in the function.

a=0;b=0;//Change in each variable

#1;//Time Delay

a=0;b=1;

#1;

a=1;b=0;

#1

a=1;b=1;

end//End of procedural block begin

endmodule//end of modules

2. Write a Verilog code that demonstrates at least seven number

representations and seven different operators in Verilog. Use the display
function to print the results of all operations.

module number_representations;
 initial begin

$display("%d",4'b1010);//Binary Representation of 10

$display("%d",12);//12 is an unsigned decimal number

$display("%d",8'd25);//25 is a decimal number which could take 8-bits

//In fact it only takes 5,but memory allocation is in multiple of 4,therefore

it takes 8 bits

$display("%d",8'hFF);//hexadecimal number of 255

$display("%d",8'o77);//octal of 77

$display("%d",16'd1234);//decimal of 1234 which takes 16 bits

$display("%d",-4'd3);//gives -3 of 4 bits in binary

end

endmodule

//Data Flow Modelling

module number_representation;

wire [7:0] add, multiply, divide, not_, xor_;

wire signed [7:0] subtract; // Use Signed wire

//if unsigned wire is used ,then it may lead to underflow

assign add = 4'b1010 + 8'd25; // 10 + 25 = 35

assign subtract = $signed(4'b1010) - 8'd25; // 10 - 25 = -15 signed used here

assign multiply = 4'b1010 * 8'd18; // 10 * 18 = 180

assign divide = 4'b1010 / 4'b0101; // 10 / 5 = 2

assign not_ = ~8'd25; // Bitwise NOT of 25

assign xor_ = 8'd25 ^ 8'hFF; // XOR of 25 and 255 (8-bit)

initial begin

$display("Addition: %d", add);

$display("Subtraction: %d", subtract);

$display("Multiplication: %d", multiply);

$display("Division: %d", divide);

$display("Bitwise NOT: %d", not_);

$display("Bitwise XOR: %d", xor_);

end

endmodule

//Gate level Modelling

module num;//Module begins

//Gate level is mostly used for 1-bit operation

wire a,b;//assigning two variables

assign a=1'b1;//a as 1

assign b=1'b0;//b as 2

wire add;//Declares wires

xor G1add_(add,a,b);//Assigns the addition to add

wire negate;

not G2not_(not_,a);

wire or_;

or G3or_(or_,a,b);

wire nand_;

nand G4nand_(nand_,a,b);
wire and_;

and G5_and_(and_,a,b);

wire nor_;

nor G6nor_(nor_,a,b);

initial begin//Beginning of thee procedural block

$display("Addition using xor result: %b", add);

$display("AND (1-bit multiplication): %b", and_);

$display("OR: %b", or_);

$display("NOT (of a): %b", not_);

$display("NAND: %b", nand_);

$display("NOR: %b", nor_);

end//Ending of the procedural block

endmodule//Module ends here

3. Write the design and testbench code for all seven basic logic gates: AND,
OR, NOT, NAND, NOR, XOR, and XNOR. Simulate the code and include
screenshots of the output.

// Behavioral Modeling for Basic Logic Gates

module and_gate(input a, input b, output reg y);//input of a and b with output

of y

always @(*) begin//asterisk as sensitivity list means any changes will be

monitored

y = a & b;

end

endmodule

module or_gate(input a, input b, output reg y);

 always @(*) begin

y = a | b;

end

endmodule

module not_gate(input a, output reg y);

always @(*) begin

y = ~a;

end

endmodule

module nand_gate(input a, input b, output reg y);

always @(*) begin

y = ~(a & b);

end

endmodule

module nor_gate(input a, input b, output reg y);

always @(*) begin

y = ~(a | b);

end

endmodule

module xor_gate(input a, input b, output reg y);

always @(*) begin

y = a ^ b;

end

endmodule
module xnor_gate(input a, input b, output reg y);

always @(*) begin

y = ~(a ^ b);

end

endmodule

//Testbench Codes

module test_gates;

reg a, b;

wire and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,

xnor_out_;//Initiallizing wire

// Instantiate the behavioral gate modules

and_gate U1(.a(a), .b(b), .y(and_out_));//,operator just assigns the values into

parameters.

or_gate U2(.a(a), .b(b), .y(or_out_));

not_gate U3(.a(a), .y(not_out_)); // NOT uses a single input

nand_gate U4(.a(a), .b(b), .y(nand_out_));

nor_gate U5(.a(a), .b(b), .y(nor_out_));

xor_gate U6(.a(a), .b(b), .y(xor_out_));

xnor_gate U7(.a(a), .b(b), .y(xnor_out_));

initial begin

$display("Nidal Noushad Roshand CS24B1039");

$display("Time a b | AND OR NOT NAND NOR XOR XNOR");

$monitor("%0t %b %b | %b %b %b %b %b %b %b",
 $time, a, b, and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,
xnor_out_);

a = 0; b = 0; #10;//Delay of 10ns

a = 0; b = 1; #10;

a = 1; b = 0; #10;

a = 1; b = 1; #10;

end

endmodule

//Dataflow Modelling

//creating each modules of each operators

module and_gate(input a, input b, output y);//input a,b and output y

assign y = a & b;

endmodule

module or_gate(input a, input b, output y);

assign y = a | b;

endmodule

module not_gate(input a, output y);

assign y = ~a;

endmodule

module nand_gate(input a, input b, output y);

assign y = ~(a & b);

endmodule

module nor_gate(input a, input b, output y);

 assign y = ~(a | b);

endmodule

module xor_gate(input a, input b, output y);

assign y = a ^ b;

endmodule

module xnor_gate(input a, input b, output y);

assign y = ~(a ^ b);

endmodule

//Now for the testbench code

//Note:Testbench codes are similar in all modelling

module test_gates;

reg a, b;

wire and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,

xnor_out_;//Initiallizing wire

// Instantiate the behavioral gate modules

and_gate U1(.a(a), .b(b), .y(and_out_));//operator just assigns the values into

parameters.

or_gate U2(.a(a), .b(b), .y(or_out_));

not_gate U3(.a(a), .y(not_out_)); // NOT uses a single input

nand_gate U4(.a(a), .b(b), .y(nand_out_));

nor_gate U5(.a(a), .b(b), .y(nor_out_));

xor_gate U6(.a(a), .b(b), .y(xor_out_));

xnor_gate U7(.a(a), .b(b), .y(xnor_out_));

initial begin
 $display("Nidal Noushad Roshan CS24B1039");

$display("Time a b | AND OR NOT NAND NOR XOR XNOR");

$monitor("%0t %b %b | %b %b %b %b %b %b %b",

$time, a, b, and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,

xnor_out_);

a = 0; b = 0; #10;//Delay of 10ns

a = 0; b = 1; #10;

a = 1; b = 0; #10;

a = 1; b = 1; #10;

end

endmodule

// Gate-Level Modeling for Basic logic Gates

module and_gate(input a, input b, output y);//Input a,b and output y

and G1(y, a, b);//G1 ,G2.... all are gates

endmodule

module or_gate(input a, input b, output y);

or G2(y, a, b);

endmodule

module not_gate(input a, output y);

not G3(y, a);

endmodule

module nand_gate(input a, input b, output y);

nand G4(y, a, b);

endmodule

module nor_gate(input a, input b, output y);

nor G5(y, a, b);

endmodule

module xor_gate(input a, input b, output y);

xor G6(y, a, b);

endmodule

module xnor_gate(input a, input b, output y);

xnor G7(y, a, b);

endmodule

//Now for the testbench code

//Note:Testbench codes are similar in all modelling

module test_gates;

reg a, b;

wire and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,

xnor_out_;//Initiallizing wire

// Instantiate the behavioral gate modules

and_gate U1(.a(a), .b(b), .y(and_out_));//,operator just assigns the values into

parameters.

or_gate U2(.a(a), .b(b), .y(or_out_));

not_gate U3(.a(a), .y(not_out_)); //'' NOT 'uses a single input

nand_gate U4(.a(a), .b(b), .y(nand_out_));

nor_gate U5(.a(a), .b(b), .y(nor_out_));

xor_gate U6(.a(a), .b(b), .y(xor_out_));

xnor_gate U7(.a(a), .b(b), .y(xnor_out_));

 initial begin

$display("Nidal Noushad Roshan CS24B1039");

$display("Time a b | AND OR NOT NAND NOR XOR XNOR");

$monitor("%0t %b %b | %b %b %b %b %b %b %b",

$time, a, b, and_out_, or_out_, not_out_, nand_out_, nor_out_, xor_out_,

xnor_out_);

a = 0; b = 0; #10;//Delay of 10ns

a = 0; b = 1; #10;

a = 1; b = 0; #10;

a = 1; b = 1; #10;

end

endmodule

4. Write the design and testbench code for: • Half Adder • Full Adder • Half
Subtractor • Full Subtractor Execute the code, capture the output, and
include screenshots.

module half_adder(

input A,//Note :these are module inputs and outputs

input B,

output reg Sum,

output reg Carry

);

always @(*) begin

Sum = A ^ B;

Carry = A & B;

end
endmodule

module full_adder(

input A,

input B,

input Cin,

output reg Sum,

output reg Carry

);

always @(*) begin

Sum = A ^ B ^ Cin;

Carry = (A & B) | (B & Cin) | (A & Cin);

end

endmodule

module half_subtractor(

input A,

input B,

output reg Diff,

output reg Borrow

);

always @(*) begin

Diff = A ^ B;

Borrow = (~A) & B;

end

endmodule
module full_subtractor(

input A,

input B,

input Bin,

output reg Diff,

output reg Borrow

);

always @(*) begin

Diff = A ^ B ^ Bin;

Borrow = ((~A) & B) | ((~A) & Bin) | (B & Bin);

end

endmodule

module test_behav;

// Signals for Half Adder

reg ha_A, ha_B;

wire ha_S, ha_C;

//Signals for Half Subtractor

reg hs_A, hs_B;

wire hs_D, hs_Bor;

// Signals for Full Adder

reg fa_A, fa_B, fa_Cin;

wire fa_S, fa_C;

//Signals for Full Subtractor

 reg fs_A, fs_B, fs_Bin;

wire fs_D, fs_Bor;

// Instantiate Behavioral Modules

half_adder HA (.A(ha_A), .B(ha_B), .Sum(ha_S), .Carry(ha_C));

half_subtractor HS (.A(hs_A), .B(hs_B), .Diff(hs_D), .Borrow(hs_Bor));

full_adder FA (.A(fa_A), .B(fa_B), .Cin(fa_Cin), .Sum(fa_S), .Carry(fa_C));

full_subtractor FS (.A(fs_A), .B(fs_B), .Bin(fs_Bin), .Diff(fs_D), .Borrow(fs_Bor));

initial begin

$display("Nidal Noushad Roshan CS24B1039");

$display("Time | HA: A B -> Sum Carry | HS: A B -> Diff Borrow | FA: A B Cin
-> Sum Carry | FS: A B Bin -> Diff Borrow");

$monitor("%0t | HA: %b %b -> %b %b | HS: %b %b -> %b %b | FA: %b %b

%b -> %b %b | FS: %b %b %b -> %b %b",

$time, ha_A, ha_B, ha_S, ha_C,

hs_A, hs_B, hs_D, hs_Bor,

fa_A, fa_B, fa_Cin, fa_S, fa_C,

fs_A, fs_B, fs_Bin, fs_D, fs_Bor);

ha_A = 0; ha_B = 0; hs_A = 0; hs_B = 0;

fa_A = 0; fa_B = 0; fa_Cin = 0;

fs_A = 0; fs_B = 0; fs_Bin = 0; #10;

ha_A = 0; ha_B = 1; hs_A = 0; hs_B = 1;

 fa_A = 0; fa_B = 0; fa_Cin = 1;

fs_A = 0; fs_B = 0; fs_Bin = 1; #10;

ha_A = 1; ha_B = 0; hs_A = 1; hs_B = 0;

fa_A = 0; fa_B = 1; fa_Cin = 0;

fs_A = 0; fs_B = 1; fs_Bin = 0; #10;

ha_A = 1; ha_B = 1; hs_A = 1; hs_B = 1;

fa_A = 1; fa_B = 1; fa_Cin = 1;

fs_A = 1; fs_B = 1; fs_Bin = 1; #10;

end

endmodule

endmodule

module full_adder(

input A,

input B,

input Cin,

output Sum,

output Carry

);

assign Sum = A ^ B ^ Cin;

assign Carry = (A & B) | (B & Cin) | (A & Cin);

endmodule

module half_subtractor(
 input A,

input B,

output Diff,

output Borrow

);

assign Diff = A ^ B;

assign Borrow = (~A) & B;

endmodule

module full_subtractor(

input A,

input B,

input Bin,

output Diff,

output Borrow

);

assign Diff = A ^ B ^ Bin;

assign Borrow = ((~A) & B) | ((~A) & Bin) | (B & Bin);

endmodule

module test_behav;

// Signals for Half Adder

reg ha_A, ha_B;

wire ha_S, ha_C;

//Signals for Half Subtractor

 reg hs_A, hs_B;

wire hs_D, hs_Bor;

// Signals for Full Adder

reg fa_A, fa_B, fa_Cin;

wire fa_S, fa_C;

//Signals for Full Subtractor

reg fs_A, fs_B, fs_Bin;

wire fs_D, fs_Bor;

// Instantiate Behavioral Modules

half_adder HA (.A(ha_A), .B(ha_B), .Sum(ha_S), .Carry(ha_C));

half_subtractor HS (.A(hs_A), .B(hs_B), .Diff(hs_D), .Borrow(hs_Bor));

full_adder FA (.A(fa_A), .B(fa_B), .Cin(fa_Cin), .Sum(fa_S), .Carry(fa_C));

full_subtractor FS (.A(fs_A), .B(fs_B), .Bin(fs_Bin), .Diff(fs_D), .Borrow(fs_Bor));

initial begin

$display("Nidal Noushad Roshan CS24B1039");

$display("Time | HA: A B -> Sum Carry | HS: A B -> Diff Borrow | FA: A B Cin
-> Sum Carry | FS: A B Bin -> Diff Borrow");

$monitor("%0t | HA: %b %b -> %b %b | HS: %b %b -> %b %b | FA: %b %b

%b -> %b %b | FS: %b %b %b -> %b %b",

$time, ha_A, ha_B, ha_S, ha_C,

hs_A, hs_B, hs_D, hs_Bor,

fa_A, fa_B, fa_Cin, fa_S, fa_C,

 fs_A, fs_B, fs_Bin, fs_D, fs_Bor);

ha_A = 0; ha_B = 0; hs_A = 0; hs_B = 0;

fa_A = 0; fa_B = 0; fa_Cin = 0;

fs_A = 0; fs_B = 0; fs_Bin = 0; #10;

ha_A = 0; ha_B = 1; hs_A = 0; hs_B = 1;

fa_A = 0; fa_B = 0; fa_Cin = 1;

fs_A = 0; fs_B = 0; fs_Bin = 1; #10;

ha_A = 1; ha_B = 0; hs_A = 1; hs_B = 0;

fa_A = 0; fa_B = 1; fa_Cin = 0;

fs_A = 0; fs_B = 1; fs_Bin = 0; #10;

ha_A = 1; ha_B = 1; hs_A = 1; hs_B = 1;

fa_A = 1; fa_B = 1; fa_Cin = 1;

fs_A = 1; fs_B = 1; fs_Bin = 1; #10;

end

endmodule

//Gate level Modelling

module half_adder(

input A,

input B,

output Sum,

output Carry
);

xor (Sum, A, B);

and (Carry, A, B);

endmodule

module full_adder(

input A,

input B,

input Cin,

output Sum,

output Carry

);

wire xor1, and1, and2, and3;//Since gate -level Model is not as sophisticated
as other models in multi bit operations

//Wires are just used to carry the outubut unlike reg

xor (xor1, A, B);//First adding up a and b and storing it in xor1

xor (Sum, xor1, Cin);//adding up cin and adding up with previous xor1

and (and1, A, B);

and (and2, A, Cin);

and (and3, B, Cin);

or (Carry, and1, and2, and3);

endmodule

module half_subtractor(

input A,
 input B,

output Diff,

output Borrow

);

wire nA;

not (nA, A);

xor (Diff, A, B);

and (Borrow, nA, B);

endmodule

module full_subtractor(

input A,

input B,

input Bin,

output Diff,

output Borrow

);

wire xor1, and1, and2, and3, nA;

xor (xor1, A, B);

xor (Diff, xor1, Bin);

not (nA, A);

and (and1, nA, B);

and (and2, nA, Bin);

and (and3, B, Bin);

 or (Borrow, and1, and2, and3);

endmodule

module test_behav;

// Signals for Half Adder

reg ha_A, ha_B;

wire ha_S, ha_C;

//Signals for Half Subtractor

reg hs_A, hs_B;

wire hs_D, hs_Bor;

// Signals for Full Adder

reg fa_A, fa_B, fa_Cin;

wire fa_S, fa_C;

//Signals for Full Subtractor

reg fs_A, fs_B, fs_Bin;

wire fs_D, fs_Bor;

// Instantiate Behavioral Modules

half_adder HA (.A(ha_A), .B(ha_B), .Sum(ha_S), .Carry(ha_C));

half_subtractor HS (.A(hs_A), .B(hs_B), .Diff(hs_D), .Borrow(hs_Bor));

full_adder FA (.A(fa_A), .B(fa_B), .Cin(fa_Cin), .Sum(fa_S), .Carry(fa_C));

full_subtractor FS (.A(fs_A), .B(fs_B), .Bin(fs_Bin), .Diff(fs_D), .Borrow(fs_Bor));

initial begin
 $display("Nidal Noushad Roshan CS24B1039");

$display("Time | HA: A B -> Sum Carry | HS: A B -> Diff Borrow | FA: A B Cin
-> Sum Carry | FS: A B Bin -> Diff Borrow");

$monitor("%0t | HA: %b %b -> %b %b | HS: %b %b -> %b %b | FA: %b %b

%b -> %b %b | FS: %b %b %b -> %b %b",

$time, ha_A, ha_B, ha_S, ha_C,

hs_A, hs_B, hs_D, hs_Bor,

fa_A, fa_B, fa_Cin, fa_S, fa_C,

fs_A, fs_B, fs_Bin, fs_D, fs_Bor);

ha_A = 0; ha_B = 0; hs_A = 0; hs_B = 0;

fa_A = 0; fa_B = 0; fa_Cin = 0;

fs_A = 0; fs_B = 0; fs_Bin = 0; #10;

ha_A = 0; ha_B = 1; hs_A = 0; hs_B = 1;

fa_A = 0; fa_B = 0; fa_Cin = 1;

fs_A = 0; fs_B = 0; fs_Bin = 1; #10;

ha_A = 1; ha_B = 0; hs_A = 1; hs_B = 0;

fa_A = 0; fa_B = 1; fa_Cin = 0;

fs_A = 0; fs_B = 1; fs_Bin = 0; #10;

ha_A = 1; ha_B = 1; hs_A = 1; hs_B = 1;

fa_A = 1; fa_B = 1; fa_Cin = 1;

fs_A = 1; fs_B = 1; fs_Bin = 1; #10;

 end

endmodule

5. Write the design and testbench code for: • 2x1 Multiplexer • 4x1 Multiplexer
Simulate the code, take a screenshot of the results, and include them in your
document.

//Multiplexer 2x1

module mux2x1(

input m0, // Data input 0

input m1, // Data input 1

input sel, // Select input

output y // Output

);

assign y = sel ? m1 : m0;

endmodule

//Multiplexer 4x1

module mux4x1(

input m0, // Data input 0

input m1, // Data input 1

input m2, // Data input 2

input m3, // Data input 3

input [1:0] sel, // 2-bit Selector

output y // Output

);

// Use nested ternary operators to choose the proper data input

//Using 3 conditional operator to take out one of four selectors.

 assign y = (sel == 2'b00) ? m0 ://Anyone of the inputs

(sel == 2'b01) ? m1 :

(sel == 2'b10) ? m2 : m3;//Anyone of inputs

endmodule

//TestBench Code

module test_mux;

// Signals for 2x1 MUX

reg mux2_m0, mux2_m1, mux2_sel;

wire mux2_out;

// Signals for 4x1 MUX

reg mux4_m0, mux4_m1, mux4_m2, mux4_m3;

reg [1:0] mux4_sel;

wire mux4_out;

// Instantiate the 2x1 multiplexer

mux2x1 M1(

.m0(mux2_m0),

.m1(mux2_m1),

.sel(mux2_sel),

.y(mux2_out)

);

// Instantiate the 4x1 multiplexer

mux4x1 M2(
 .m0(mux4_m0),

.m1(mux4_m1),

.m2(mux4_m2),

.m3(mux4_m3),

.sel(mux4_sel),

.y(mux4_out)

);

initial begin

$display("Nidal Noushad Roshan CS24B1039");

$display("Time | 2x1 MUX: d0 d1 sel -> y | 4x1 MUX: d0 d1 d2 d3 sel -> y");

$monitor("%0t | 2x1: %b %b %b -> %b | 4x1: %b %b %b %b %b -> %b",

$time, mux2_m0, mux2_m1, mux2_sel, mux2_out,

mux4_m0, mux4_m1, mux4_m2, mux4_m3, mux4_sel, mux4_out);

mux2_m0 = 0; mux2_m1 = 1; mux2_sel = 0;//this chooses m0

mux4_m0 = 0; mux4_m1 = 1; mux4_m2 = 0; mux4_m3 = 1; mux4_sel =

2'b00;//this chooses m0

#10;

mux2_sel = 1; // this should select m1 by the same test inputs given before
OR CAN SAY IT SWITCHED

mux4_sel = 2'b01; // this should select m1

#10;

mux2_m0 = 1; mux2_m1 = 0;

mux4_m0 = 1; mux4_m1 = 0; mux4_m2 = 1; mux4_m3 = 0; mux4_sel =

2'b10; // selects m2

#10;
 mux2_sel = 0;

mux4_sel = 2'b11; // For 4x1, should select m3

#10;

end

endmodule

//Gate Level Modelling

//Multiplexer 2x1

module mux2x1(

input m0,

input m1,

input sel,

output y

);

wire nsel, y0, y1;

not (nsel, sel);

and (y0, m0, nsel);

and (y1, m1, sel);

or (y, y0, y1);

endmodule

//Multiplexer 4x1

module mux4x1(

input m0,

input m1,

input m2,
 input m3,

input [1:0] sel,

output y

);

wire nsel0, nsel1;

wire y0, y1, y2, y3;

not (nsel0, sel[0]);

not (nsel1, sel[1]);

and (y0, m0, nsel1, nsel0); // When sel == 00

and (y1, m1, nsel1, sel[0]); // When sel == 01

and (y2, m2, sel[1], nsel0); // When sel == 10

and (y3, m3, sel[1], sel[0]); // When sel == 11

or (y, y0, y1, y2, y3);

endmodule

//TestBench Code

module test_mux;

// Signals for 2x1 MUX

reg mux2_m0, mux2_m1, mux2_sel;

wire mux2_out;

// Signals for 4x1 MUX

reg mux4_m0, mux4_m1, mux4_m2, mux4_m3;

reg [1:0] mux4_sel;

wire mux4_out;

// Instantiate the 2x1 multiplexer

 mux2x1 M1(

.m0(mux2_m0),

.m1(mux2_m1),

.sel(mux2_sel),

.y(mux2_out)

);

// Instantiate the 4x1 multiplexer

mux4x1 M2(

.m0(mux4_m0),

.m1(mux4_m1),

.m2(mux4_m2),

.m3(mux4_m3),

.sel(mux4_sel),

.y(mux4_out)

);

initial begin

$display("Nidal Noushad Roshan CS24B1039");

$display("Time | 2x1 MUX: d0 d1 sel -> y | 4x1 MUX: d0 d1 d2 d3 sel -> y");

$monitor("%0t | 2x1: %b %b %b -> %b | 4x1: %b %b %b %b %b -> %b",

$time, mux2_m0, mux2_m1, mux2_sel, mux2_out,

mux4_m0, mux4_m1, mux4_m2, mux4_m3, mux4_sel, mux4_out);

mux2_m0 = 0; mux2_m1 = 1; mux2_sel = 0;//this chooses m0

mux4_m0 = 0; mux4_m1 = 1; mux4_m2 = 0; mux4_m3 = 1; mux4_sel =

2'b00;//this chooses m0
 #10;

mux2_sel = 1; // this should select m1 by the same test inputs given before
OR CAN SAY IT SWITCHED

mux4_sel = 2'b01; // this should select m1

#10;

mux2_m0 = 1; mux2_m1 = 0;

mux4_m0 = 1; mux4_m1 = 0; mux4_m2 = 1; mux4_m3 = 0; mux4_sel =

2'b10; // selects m2

#10;

mux2_sel = 0;

mux4_sel = 2'b11; // For 4x1, should select m3

#10;

end

endmodule

//Multiplexer 2x1

module mux2x1(

input m0, // Data input 0

input m1, // Data input 1

input sel, // Select input

output reg y // Output

);

always @(*) begin

if (sel)

y = m1;

else
 y = m0;

end

endmodule

//Multiplexer 4x1

module mux4x1(

input m0, // Data input 0

input m1, // Data input 1

input m2, // Data input 2

input m3, // Data input 3

input [1:0] sel, // 2-bit Selector

output reg y // Output

);

always @(*) begin

case(sel)

2'b00: y = m0;

2'b01: y = m1;

2'b10: y = m2;

2'b11: y = m3;

endcase

end

endmodule

//TestBench Code

module test_mux;

// Signals for 2x1 MUX

reg mux2_m0, mux2_m1, mux2_sel;

wire mux2_out;

// Signals for 4x1 MUX

reg mux4_m0, mux4_m1, mux4_m2, mux4_m3;

reg [1:0] mux4_sel;

wire mux4_out;

// Instantiate the 2x1 multiplexer

mux2x1 M1(

.m0(mux2_m0),

.m1(mux2_m1),

.sel(mux2_sel),

.y(mux2_out)

);

// Instantiate the 4x1 multiplexer

mux4x1 M2(

.m0(mux4_m0),

.m1(mux4_m1),

.m2(mux4_m2),

.m3(mux4_m3),

.sel(mux4_sel),

.y(mux4_out)

);

initial begin

$display("Nidal Noushad Roshan CS24B1039");

 $display("Time | 2x1 MUX: d0 d1 sel -> y | 4x1 MUX: d0 d1 d2 d3 sel -> y");

$monitor("%0t | 2x1: %b %b %b -> %b | 4x1: %b %b %b %b %b -> %b",

$time, mux2_m0, mux2_m1, mux2_sel, mux2_out,

mux4_m0, mux4_m1, mux4_m2, mux4_m3, mux4_sel, mux4_out);

mux2_m0 = 0; mux2_m1 = 1; mux2_sel = 0;//this chooses m0

mux4_m0 = 0; mux4_m1 = 1; mux4_m2 = 0; mux4_m3 = 1; mux4_sel =

2'b00;//this chooses m0

#10;

mux2_sel = 1; // this should select m1 by the same test inputs given before
OR CAN SAY IT SWITCHED

mux4_sel = 2'b01; // this should select m1

#10;

mux2_m0 = 1; mux2_m1 = 0;

mux4_m0 = 1; mux4_m1 = 0; mux4_m2 = 1; mux4_m3 = 0; mux4_sel =

2'b10; // selects m2

#10;

mux2_sel = 0;

mux4_sel = 2'b11; // For 4x1, should select m3

#10;

end

endmodule