Principle of Microcomputer

Based on ARM Technology

STM32 GPIO
CONTENTS
• Objectives

• GPIO Features

• GPIO Configuration Modes

• Structure of STM32 GPIO

• STM32 GPIO Configuration

• STM32 GPIO Application

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★Objectives:

▪ Know STM32 GPIOs features and modes

▪ Grasp the structures of STM32 GPIO.

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GPIO Features
• Bi-directional I/O ports available
• Standard I/Os 5V tolerant
• The GPIOs can sink 25mA
• 18 MHz Toggling
• Configurable Output Speed up to 50 MHz
• Up to 16 Analog Inputs
• Alternate Functions pins (like USARTx, TIMx, I2Cx,
SPIx,…)

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GPIO Features
• Bi-directional I/O ports available
• Can be set-up as external interrupt
• One I/O can be used as Wake-Up from STANDBY (PA.00)
• One I/O can be set-up as Tamper Pin (PC.13)
• All Standard I/Os are shared in 5 ports (GPIOA..GPIOE)
• Locking mechanism to avoid spurious write in the IO
registers:
When the LOCK sequence has been applied on a port
bit, it is no longer possible to modify the configuration
of the port bit until the next reset (no write access to
the CRL and CRH registers corresponding bit).
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 STM32 GPIO and pins

STM32 microcontroller has seven ports: PA,

PB, PC, PD, PE, PF, PG.

STM32F103VET6 has five 16-bit ports: PA, PB, PC, PD, PE.

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•STM32F103VET6 pins

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GPIO Configuration Modes
Subject to the specific hardware characteristics of each I/O port listed in the
datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be
individually configured by software in several modes:

● Input floating
● Input pull-up
● Input-pull-down
● Analog
● Output open-drain
● Output push-pull
● Alternate function push-pull
● Alternate function open-drain

Each I/O port bit is freely programmable, however the I/O port registers have to
be accessed as 32-bit words (half-word or byte accesses are not allowed). The
purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic
read/modify accesses to any of the GPIO registers. This way, there is no risk that
an IRQ occurs between the read and the modify access.

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GPIO Configuration Modes

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GPIO Configuration Modes

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GPIO Configuration Modes

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AFIO Features/ GPIO Remapping(1/3)
• To optimize the number of peripherals available for the 64-pin or the 100-
pin or the 144-pin package, it is possible to remap some alternate
functions to some other pins. This is achieved by software, In this case, the
alternate functions are no longer mapped to their original assignations.

Note: For more details please refer to Datasheet

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AFIO Features/ GPIO Remapping(2/3)
• Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1
The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-
purpose I/O PD0/PD1by programming the PD01_REMAP bit in the AF
remap and debug I/O configuration register (AFIO_MAPR).
• Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose I/O
PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the
GPIOs function.

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AFIO Features/ GPIO Remapping(3/3)
▪ Using Debug pins:

▪ To optimize the number of free

GPIOs during debugging, this
mapping can be configured in
different ways by programming the
SWJ_CFG[1:0] bits in the AF remap
and debug I/O configuration
register (AFIO_MAPR).

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Circuit structure of STM32 GPIO
1. Input configuration Pull-up, pull-down or
Floating, pull-up or pull-down input floating can be set
according to the
Schmitt trigger is on requirement.

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Output buffer is disabled
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 When the I/O Port is programmed as Input:

⚫ The Output Buffer is disabled

⚫ The Schmitt Trigger Input is activated
⚫ The weak pull-up and pull-down resistors are activated
or not depending on input configuration (pull-up, pull-
down or floating)
⚫ The data present on the I/O pin is sampled into the Input
Data Register every APB2 clock cycle
⚫ A read access to the Input Data Register obtains the I/O
State.

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2. Output configuration Schmitt trigger is on

In open-drain mode, P-MOS is not activated, and only N-MOS works. ‘0’
on the output register will activate N-MOS, and output LOW, and ‘1’ on the
output register will set the port to high impedance status.
In push-pull mode, ‘0’ on the output register will activate N-MOS, and ‘1’
on the output register will activate P-MOS. 17
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When the I/O Port is programmed as Output:
● The Output Buffer is enabled:
– Open Drain Mode: A “0” in the Output register activates the N-MOS
while a “1” in the Output register leaves the port in Hi-Z. (the P-MOS
is never activated)
– Push-Pull Mode: A “0” in the Output register activates the N-MOS
while a “1” in the Output register activates the P-MOS.
● The Schmitt Trigger Input is activated.
● The weak pull-up and pull-down resistors are disabled.
● The data present on the I/O pin is sampled into the Input Data
Register every APB2 clock cycle
● A read access to the Input Data Register gets the I/O state in open
drain mode
● A read access to the Output Data register gets the last written value
in Push-Pull mode

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3. Alternate function configuration
Pull-up and pull-down are
Alternate function input Schmitt trigger is on
disabled.

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When the I/O Port is programmed as Alternate Function:

● The Output Buffer is turned on in Open Drain or Push-Pull

configuration
● The Output Buffer is driven by the signal coming from the peripheral
(alternate function out)
● The Schmitt Trigger Input is activated
● The weak pull-up and pull-down resistors are disabled.
● The data present on the I/O pin is sampled into the Input Data
Register every APB2 clock cycle
● A read access to the Input Data Register gets the I/O state in open
drain mode
● If a port is configured as alternate output function, the pin will
disconnected with output register, the signal comes from on-chip
peripherals output.

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STM32 GPIO Configuration

(1) Port configuration register low (GPIOx_CRL) (x=A..G)

(2) Port configuration register high (GPIOx_CRH) (x=A..G)

(3) Port input data register (GPIOx_IDR) (x=A..G)

(4) Port output data register (GPIOx_ODR) (x=A..G)

(5) Port bit set/reset register (GPIOx_BSRR) (x=A..G)

(6) Port bit reset register (GPIOx_BRR) (x=A..G)

(7) Port configuration lock register (GPIOx_LCKR) (x=A..G)

The peripheral registers have to be accessed by words (32-bit).

Every bit definition of every register is shown in Reference manual
from page 159.
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