EE1005 – Digital Logic Design

Lecture 13
 Outline
• Exclusive OR (XOR) Function
– Properties of XOR
– Applications of XOR
– Parity Generator and Checker
• Exclusive NOT OR (XNOR) Function

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 2

 Exclusive OR Function (XOR)
• The Exclusive-OR (XOR) is denoted by ⊕ and
performs the following logical operation
A ⊕ B = AB’ + A’B

A B A’ B’ AB’ A’B A⊕B

0 0 1 1 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 0 0 0 0 0

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 3

 XOR with Three Inputs
F=A⊕B⊕C
F = (A ⊕ B) ⊕ C A B C A⊕B⊕C
0 0 0 0
F = (AB’ + A’B) ⊕ C 0 0 1 1
0 1 0 1
F = (AB’ + A’B)C’ + (AB + A’B’)C 0 1 1 0
F = AB’C’ + A’BC’ + ABC + A’B’C 1 0 0 1
1 0 1 0
F = Σ(1, 2, 4, 7) 1 1 0 0
1 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 4

 XOR with Four Inputs
F=A⊕B⊕C⊕D A B C D A⊕B⊕C⊕D
0 0 0 0 0
F = (A ⊕ B) ⊕ (C ⊕ D) 0 0 0 1 1
F = (AB’ + A’B) ⊕ (CD’ + C’D) 0 0 1 0 1
F = Σ(1, 2, 4, 7, 8, 11, 13, 14) 0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
XOR is an ODD function 0 1 1 0 0
If number of 1’s in the input stream 0 1 1 1 1
are odd then the output is 1, 1 0 0 0 1
otherwise the output is 0 1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
The complement of XOR is XNOR 1 1 0 0 0
and is EVEN function 1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 5
 Properties of XOR Function
• It is an ODD function
• A⊕0=A
• A ⊕ 1 = A’
• A⊕A=0
• A ⊕ A’ = 1
• A ⊕ B’ = A’ ⊕ B = (A ⊕ B)’
• XOR is commutative
A⊕B=B⊕A
• XOR is associative
(A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) = A ⊕ B ⊕ C

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 6

 2 Input XOR and XNOR
XOR XNOR
A ⊕ B = A’B + AB’ (A⊕B)’ = AB + A’B’

A B (A ⊕ B) A B (A ⊕ B)’
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 7
 Applications of XOR
• Binary Arithmetic
• Parity Generation
• Parity Checking
• Controlled Inverter
• Digital Comparator
• Binary to Gray/Gray to Binary Conversion
• Letter case conversion (upper to lower or
lower to upper)

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 8

 Parity Generation and Checking
• Exclusive-OR functions are very useful in systems
requiring error detection and correction codes
• This is done with the help of a parity bit
– The parity bit is an extra bit added to the original message to
make the number of 1’s even or odd
– Parity bit is added at MSB position
– For example the message 011 0010 will be written as
1011 0010 with even parity and
0011 0010 with odd parity
• The circuit that generates the parity bit in the transmitter
is called a parity generator
• The circuit that checks the parity in the receiver is called
a parity checker

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 9

 Parity Generator and Checker (1/4)

• x,y, and z are inputs

• For even parity the number of 1’s including
Parity bit (P) must be even
P=x⊕y⊕z
• For parity checker the inputs are x, y, z, and
P and the output is 1 if the number of 1’s
are odd, which means that an error has
occurred
C=x⊕y⊕z⊕P
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 10
 Parity Generator and Checker (2/4)

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 Parity Generator and Checker (3/4)

Truth table of 3 bit parity checker

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 12
 Parity Generator and Checker (4/4)
• The parity generator can be implemented with the
circuit of parity checker
• This can be done by connecting the input P with the
logic 0 and marking the output as P

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 13

 Case Conversion
• If we label the bits in ASCII codes from b0 to b7 (b0 as LSB
and b7 as MSB)
• And observe the ASCII codes of lower- and upper-case
letters, then we see that:
– Bit number 5 is 0 in upper-case letters
– Bit number 5 is 1 in lower-case letters
– All other bits are same
• For example, the ASCII codes of
– A= (41)16 = 0 1 0 0 0 0 0 1
– a = (61)16 = 0 1 1 0 0 0 0 1
• Hence, we just need to invert b5 to convert from upper to
lower, or lower to upper case while keeping all other bits
unchanged.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 14

 Practice Problem 1
Use Boolean algebra to show that
(A ⊕ B)’ = AB + A’B’

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 15

 Practice Problem 2
• Prove that the following circuit is equivalent
to a XOR function.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 16

EE1005 – Digital Logic Design

Lecture 14
 Outline
• Types of logical circuits
– Combinational
– Sequential
• Analysis Procedure for Combinational
Circuits
• Design Procedure for Combinational Circuits
• Designing a Half Adder
• Designing a Full Adder
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 18
 Types of Logical Circuits
• Logic circuits for digital systems may be:
– Combinational
• A combinational circuit consists of logic gates whose
outputs at any time are determined from only the
present combination of inputs
– Sequential
• Sequential circuits employ storage elements in
addition to logic gates. Their outputs are a function
of the inputs and the state of the storage elements
• The outputs of a sequential circuit depend not only
on present values of inputs, but also on past inputs

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 19

 Combinational Circuits
• A combinational circuit consists of an interconnection of
logic gates
• A block diagram of a combinational circuit is shown

• The n input binary variables come from an external

source; the m output variables are produced by the
internal combinational logic circuit and go to an external
destination
• Inputs and outputs are physical signals

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 20

 Representations of a
Combinational Circuit
• A combinational circuit with “n” inputs and “m”
outputs can be represented by
• Circuit Diagram
• Truth Table
– n inputs so there are 2n possible combinations
– Truth table will contain 2n rows
• Boolean Functions
– m outputs
– One function for each output so m Boolean functions
– Each output function is expressed in terms of the n
input variables
• Timing Diagram

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 21

 Standard Combinations Circuits
• There are several combinational circuits that
are employed extensively in the design of
digital systems
• These circuits are available in integrated circuits
and are classified as standard components
• Here, we will discuss the most important
standard combinational circuits, such as adders,
subtractors, comparators, decoders, encoders,
and multiplexers

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 22

 Analysis Procedure (1/2)
• The analysis of a combinational circuit requires that we
determine the function that the circuit implements
• Given
– A circuit diagram
• Required
– Set of Boolean functions
– Truth Table/Timing Diagram
– An explanation of circuit operation
• The first step in the analysis is to make sure that the
given circuit is combinational and not sequential
• The diagram of a combinational circuit has logic gates
with no feedback paths or memory elements
• A feedback path is a connection from the output of one
gate to the input of a second gate

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 23

 Analysis Procedure (2/2)
• Once the logic diagram is verified to be that of a
combinational circuit, one can proceed
• To obtain the output Boolean functions from a logic
diagram, we proceed as follows:
1. Label all gate outputs that are a function of input variables
with arbitrary symbols and determine the Boolean
functions for each gate output
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find
the Boolean functions for these gates
3. Repeat the process outlined in step 2 until the outputs of
the circuit are obtained
4. By repeated substitution of previously defined functions,
obtain the output Boolean functions in terms of input
variables

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 24

 Example 1
• Obtain the Boolean Expression and Truth Table
of the following circuit

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 25

 Example 1
• Obtain the Boolean Expression and Truth Table
of the following circuit
T1
ABC
F 1 = T1 + T3
T2
A+B+C
T3
(T2)(F2)’
(F2)’
AB

AC
F2 = AB + AC + BC

BC
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 26
 Obtaining the Boolean Functions
F2 = AB + AC + BC

F1 = T1 + T3

F1 = ABC + (T2. F2’)

F1 = ABC + [{A + B + C}.{(AB + AC + BC)’}]

F1 = ABC + [{A + B + C}.{(A’+B’)(A’+C’)(B’+C’)}]
F1 = ABC + [{A+B+C}{A’B’+A’C’+A’B’C’+A’C’+A’B’+A’B’C’+B’C’}]
F1 = ABC + [(A+B+C)(A’B’+A’C’+B’C’+A’B’C’)]
F1 = ABC + A’B’C + A’BC’ + AB’C’

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 27

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3

A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 28

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing AB, AC and BC
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 1
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 1 0 0
1 1 1 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 29

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing F2
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 0 0 0
1 0 1 0 1 0 1
1 1 0 1 0 0 1
1 1 1 1 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 30

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing F2’
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 1
0 1 0 0 0 0 0 1
0 1 1 0 0 1 1 0
1 0 0 0 0 0 0 1
1 0 1 0 1 0 1 0
1 1 0 1 0 0 1 0
1 1 1 1 1 1 1 0

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 31

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing T1 and T2
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0 0 1 0 0
0 0 1 0 0 0 0 1 0 1
0 1 0 0 0 0 0 1 0 1
0 1 1 0 0 1 1 0 0 1
1 0 0 0 0 0 0 1 0 1
1 0 1 0 1 0 1 0 0 1
1 1 0 1 0 0 1 0 0 1
1 1 1 1 1 1 1 0 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 32

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing T3
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0 0 1 0 0 0
0 0 1 0 0 0 0 1 0 1 1
0 1 0 0 0 0 0 1 0 1 1
0 1 1 0 0 1 1 0 0 1 0
1 0 0 0 0 0 0 1 0 1 1
1 0 1 0 1 0 1 0 0 1 0
1 1 0 1 0 0 1 0 0 1 0
1 1 1 1 1 1 1 0 1 1 0

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 33

 Obtaining the Truth Table
F2 = AB + AC + BC T1 = ABC T2 = A+B+C
T3 = (T2)(F2)’ F 1 = T1 + T3
Computing F1
A B C AB AC BC F2 F2’ T1 T2 T3 F1
0 0 0 0 0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 1 0 1 1 1
0 1 0 0 0 0 0 1 0 1 1 1
0 1 1 0 0 1 1 0 0 1 0 0
1 0 0 0 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0 0 1 0 0
1 1 1 1 1 1 1 0 1 1 0 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 34

 Description of Circuit
• The given combinational
circuit is representing a full A B C F1 F2
0 0 0 0 0
adder 0 0 1 1 0
– Where A, B, and C are inputs 0 1 0 1 0
– F1 is the sum bit 0 1 1 0 1
1 0 0 1 0
– F2 is carry 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 35

 Practice Problem 1
• Analyze the following combinational circuit to find:
a) Boolean functions of outputs
b) Truth Table
c) Purpose of this combinational circuit

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 36

 Design Procedure
• The design of combinational circuits starts from
the specification of the design objective and the
procedure involves the following steps
1. Determine the required number of inputs and
outputs and assign a symbol to each
2. Derive the truth table that defines the required
relationship between inputs and outputs
3. Obtain the simplified Boolean functions for each
output as a function of the input variables
4. Draw the logic diagram and verify the correctness
of the design

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 37

 Practical Design Considerations
• Several Boolean functions may be possible for same
description
• A practical design must consider such constraints as:
– The number of gates
– Number of inputs to a gate
– Propagation time of the signal through the gates
– Number of interconnections
– Limitations of the driving capability of each gate
– Any other criteria when designing integrated circuits
• Since the importance of each constraint is dictated by
the particular application, it is difficult to make a general
statement about what constitutes an acceptable
implementation

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 38

 Binary Adder
• Digital computers perform a variety of
information-processing tasks
• Among the functions encountered are the various
arithmetic operations
• The most basic arithmetic operation is the addition of
two binary digits
• Binary numbers are added bit by bit
• To add two binary numbers, we need to add two or three
bits at a time
– A combinational circuit that performs the addition of two bits
is called a half adder
– One that performs the addition of three bits (two significant
bits and a previous carry) is a full adder

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 39

 Designing a Half Adder (1/4)
• Description
– A half adder is capable of adding two bits at a
time and produce a sum and a carry
• Input(s)/Output(s)
– 2 Inputs
• x and y
– 2 Outputs
• S and C

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 40

 Designing a Half Adder (2/4)
• Truth Table
x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 41

 Designing a Half Adder (3/4)
• Boolean Expressions of Output(s)
x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
• From truth table we can write
▪ S = x’y + xy’
▪ C = xy
• No further simplification is possible

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 42

 Designing a Half Adder (4/4)
• Circuit Diagram
S = x’y + xy’ C = xy
Number of Gates can be reduced
S = x’y + xy’
S=x⊕y
x
y S

• 6 gates are used

▪ 2 NOT gates
▪ 3 AND gates C
▪ 1 OR gate
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 43
 Designing a Full Adder (1/4)
• Description
– A full adder is capable of adding three bits at a
time and produce a sum and a carry
• Input(s)/Output(s)
– 3 Inputs
• x, y and z
– 2 Outputs
• S and C

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 44

 Designing a Full Adder (2/4)
• Truth Table
x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 45
 Designing a Full Adder (3/4)
• Boolean Expressions of Outputs
• For S x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
– S = xy’z’ + x’yz’ + xyz + x’y’z
0 1 1 0 1
• For C 1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
– C = xz + yz + xy 1 1 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 46

 Designing a Full Adder (4/4)
• Circuit Diagram
S = xy’z’ + x’yz’ + xyz + x’y’z C = xz + yz + xy

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 47

 Full Adder with Half Adders (1/2)
S=x⊕y⊕z C = xy + z(x ⊕ y)
x x⊕y
x⊕y⊕z=S
y
xy
(x ⊕ y)z

z (x ⊕ y)z + xy = C

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 48

 Full Adder with Half Adders (2/2)
• A full adder can be made by combining two half
adders with an OR gate
S = xy’z’ + x’yz’ + xyz + x’y’z
S=x⊕y⊕z

C = xz + yz + xy
C = xy + z(x + y)
C = xy + z[x(y + y’) + y(x + x’)]
C = xy + z[xy + xy’ + xy + x’y]
C = xy + xyz + xy’z + x’yz
C = xy(1 + z) + z(xy’ + x’y)
C = xy + z(x ⊕ y)
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 49
 Practice Problem 1
• Design a Half Subtractor.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 50

 Practice Problem 2
• Design a Full Subtractor.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 51

 Practice Problem 3
• Design a Full Subtractor by using Half
Subtractors.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 52

 Practice Problem 4
• In a quiz competition, there are four judges,
and a participant will qualify for the next
round if two or more judges approve his/her
answers. Design a combinational circuit that
will turn ON a buzzer after the approval of
two or more judges.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 53