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TP3: Computer Architecture

The document discusses the role of buses in CPU architecture, detailing the differences between address, data, and control buses. It explains various CPU components such as the Accumulator, Instruction Register, and Memory Address Register, along with their functions in executing arithmetic and logic operations. Additionally, it outlines the fetch-decode-execute cycle with examples of instruction execution in the smz32v50 simulator.

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Da Vy
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13 views4 pages

TP3: Computer Architecture

The document discusses the role of buses in CPU architecture, detailing the differences between address, data, and control buses. It explains various CPU components such as the Accumulator, Instruction Register, and Memory Address Register, along with their functions in executing arithmetic and logic operations. Additionally, it outlines the fetch-decode-execute cycle with examples of instruction execution in the smz32v50 simulator.

Uploaded by

Da Vy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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TP3: Computer Architecture

1. What is the role of a bus in a CPU, and why is it crucial for computer operation?
2. Explain the differences between the CPUs address bus, data bus, and control bus.
3. Research question: How do modern CPUs efficiently manage high-speed data
transfers using bus architectures like PCIe or HyperTransport? (researching question)
4. What are arithmetic operations? Please provide examples of these operations and
describe what they do.
5. What are logic operations? Please provide an example of these operations and
explain what they do.
6. Describe the role of the Accumulator (AC) register in arithmetic and logic operations.
7. What is the purpose of What is the Instruction Register (IR), and how does it help in
executing instructions?
8. Explain how the status or flag register operates and how it aids in decision-making
within the CPU.
9. What is the memory address register, And what is the function of the memory
address register (MAR)?
10. What is the memory buffer register, And what is the function of the memory buffer
register (MBR or memory data register MAR) ?
11. Please explain the instruction below with the flow of smz32v50 (simulator test) (fetch-
decode-execute in smz32v50):
Assume we have:
- First instructions:
MOV AL, 2:
ADD AL, 3:
- Second instructions: - Third instructions:
MOV AL, 2: MOV CL, 4:
PUSH AL: MOV BL, 2:
MOV BL, 2: DIV AL, BL:
MUL AL, BL:
POP AL:
ANSWER

1. Role of a Bus in a CPU & Its Importance


A bus is a communication pathway that transfers data, addresses, and control signals between
different components of the computer, such as the CPU, memory, and peripherals. It is crucial
because it ensures efficient data flow and coordination, allowing the CPU to fetch, process,
and store information.

2. Differences Between Address Bus, Data Bus, and Control Bus


- Address Bus: Carries memory addresses from the CPU to access specific locations in RAM or
I/O devices (unidirectional).
- Data Bus: Transfers actual data between the CPU, memory, and peripherals (bidirectional).
- Control Bus: Sends control signals (e.g., read/write) to manage operations between
components.

3. Efficient High-Speed Data Transfers in Modern CPUs


Modern CPUs use PCIe (Peripheral Component Interconnect Express) and Hyper Transport to
enhance data transfer efficiency.
- PCIe: Uses multiple lanes to allow parallel data transmission, reducing bottlenecks.
- Hyper Transport: Provides high-speed, low-latency communication between CPU and
chipset, optimizing system performance.

4. Arithmetic Operations & Examples


Arithmetic operations perform mathematical calculations:
- Addition (+): 5 + 3 = 8
- Subtraction (-): 9 - 4 = 5
- Multiplication (*): 6 * 2 = 12
- Division (/): 8 / 2 = 4
These operations are essential for numerical computations.
5. Logic Operations & Examples
Logic operations compare values and return true (1) or false (0):
- AND (&): 1 & 0 = 0 (both must be 1)
- OR ( | ): 1 | 0 = 1 (at least one is 1)
- XOR (^): 1 ^ 1 = 0 (different values return 1)
- NOT (~): ~1 = 0 (inverts the value)
Used in decision-making and conditional checks in programming.

6. Role of the Accumulator (AC) Register


The Accumulator (AC) register is a special CPU register that stores intermediate arithmetic and
logic results. It reduces memory access by keeping frequently used data inside the CPU for
faster calculations.

7. Purpose & Function of the Instruction Register (IR)


The Instruction Register (IR) holds the current instruction fetched from memory. It helps in
execution by passing the instruction to the control unit, which decodes and executes it.

8. Operation of the Status/Flag Register


The Status (or Flag) Register stores flags that indicate the result of operations, such as:
- Zero flag (ZF) – Set if the result is zero.
- Carry flag (CF) – Set if there is an overflow in addition/subtraction.
- Sign flag (SF) – Indicates if the result is negative.
It aids in decision-making for conditional operations.

9. Memory Address Register (MAR) & Its Function


The MAR holds the address of the memory location where data needs to be read or written. It
ensures the CPU accesses the correct memory location.

10. Memory Buffer Register (MBR) & Its Function


The MBR (also called MDR - Memory Data Register) temporarily stores data being transferred
between memory and the CPU. It acts as a buffer for efficient data exchange.
11. Explain the instruction Execution in SMZ32V50 (Fetch-Decode-Execute Cycle)
First Instructions:
MOV AL, 2 : Load AL with 2
ADD AL, 3 : Add 3 to AL

Flow:
1. Fetch: CPU fetches MOV AL, 2 → and stores 2 in AL.
2. Decode: it decodes ADD AL, 3.
3. Execute: and then adds 3 to AL, updating AL to 5.

Second Instructions:
MOV AL, 2 : Load AL with 2
PUSH AL : Store AL in stack
MOV BL, 2 : Load BL with 2
MUL AL, BL : Multiply AL by BL
POP AL : Retrieve AL from stack

Flow:
1. Fetch: CPU loads MOV AL, 2.
2. Decode & Execute: Stores AL (2) in the stack.
3. Fetch: Loads BL = 2.
4. Execute: AL * BL = 4.
5. POP AL: Restores AL from stack (back to 2).

Third Instructions:
MOV CL, 4 : Load CL with 4
MOV BL, 2 : Load BL with 2
DIV AL, BL : Divide AL by BL

Flow:
1. Fetch: MOV CL, 4 → CL = 4.
2. Fetch: MOV BL, 2 → BL = 2.
3. Decode & Execute: AL / BL → AL stores quotient, remainder in another register.

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