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Carsten Nitsch, Dr. Karlheinz Weiss, Thorsten Steckstor, Prof. Dr. Wolfgang Rosenstiel

Forschungszentrum Informatik (FZI), Embedded System Design Group, Haid-und-Neu-Straße 10, D-76131 Karlsruhe
and the University of Tübingen, Technical Computer Science, Sand 13, D-72076 Tübingen, Germany

[email protected], [email protected], [email protected], [email protected]

Abstract 2.1 Hardware First Approach

The most commonly applied methodology in industry is
This paper presents a new approach to the design of
based on a sequential design flow. The first step of this approach
embedded systems. Due to restrictions that state-of-the- is the specification of the embedded system, regarding function-
art methodologies contain for hardware/software parti- ality, power consumption, costs, etc. After completing this spec-
tioning, we have developed an emulation based method ification, a step called „partitioning“ follows. The design will be
using the facilities of reconfigurable hardware compo- separated into two parts:
nents, like Field Programmable Gate Arrays (FPGA). • A hardware part, that deals with the functionality imple-
Our own emulation environment called the SPYDER tool mented in hardware add-on components like ASICs or IP
set was used; it is best suited for the emulation of hard- cores.
ware designs for embedded systems. • A software part, that deals with code running on a micro-
controller, running alone or together with an real-time-oper-
ating system (RTOS)

1 Introduction The second step is mostly based on the experience and intu-
ition of the system designer. After completing this step, the com-
Developers of embedded systems1 have to design low cost, plete hardware architecture will be designed and implemented.
high performance systems and reduce the time-to-market to a After the target hardware is available, the software partitioning
minimum. The most important task a specification must com- can be implemented. The last step of this sequential methodolo-
plete is the partitioning of the system into two parts.The first part gy is the testing of the complete system, that means the evalua-
is the software which runs on a microcontroller. Powerful on- tion of the behavior of all the hardware and software
chip features, like data and instruction caches and higher clock components. Unfortunately developers can only verify the cor-
frequencies, speed up performance significantly. These hard- rectness of their hardware/software partitioning in this late de-
ware fundamentals allow Real-time Operating Systems (RTOS) velopment phase. If there are any uncorrectable errors, the
to be implemented, which leads to the rapid increase of total sys- design flow must restart from the beginning, which can result in
tem performance and functional complexity. Nevertheless, if enormous costs. For this reason, developers often use „well-
fast reaction times must be guaranteed, the software overhead known“ components rather then new available circuits. They
due to task switching becomes a limiting performance factor and want to reduce the risk of design faults and to reuse existing
application-specific hardware must be implemented. Due to the know-how. This is especially important for the design of sys-
decreasing life cycles of many high-end electronic products, tems consisting of few, but highly complex components. Anoth-
there is a gap between the enormous development costs and lim- er disadvantage of this approach is that it is not possible to start
ited reuse of an ASIC. In the last few years, so-called IP-Core software development before the design and test of the hardware
components became more and more popular. They offer the pos- architecture has finished. Software developers have to wait until
sibility of reusing hardware components in the same way as soft- a bug-free hardware architecture is available. Once again, the
ware libraries. In order to create such IP-Core components, the disadvantages of this methodology are: complete redesign in
system designer uses Field Programmable Gate Arrays instead case of design faults, reduced degrees of freedom in selection of
of ASICs. The designer still must partition the system design components (due to reuse of knowledge and experiences) and
into a hardware specific part and a microcontroller based part. time delays. Nonetheless, the hardware-first approach is still a
valueable approach to system design with low or medium com-
plexity, because the initial step of partitioning is less time-con-
2 State of the Art suming than in other approaches. For high-end embedded
systems new methods are needed to recognize errors during an
early phase of the design process.

1This work was supported in part with funds from the Deutsche For- 2.2 Hardware / Software Co-Design
schungsgemeinschaft under reference number 3221040 within the pri-
ority program “Design and Design Methodology of Embedded The first step in this approach focuses on a formal specifica-
Systems”. tion of a system design. Using several of the methods from

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 mathematics and computer sciences, this methodology tries to tems consisting of only a few, but nonetheless highly complex
build a complete description of the system’s behavior. The result components. Due to these analyses, we have developed another
is a decomposition of the system’s functional behavior, it takes the methodology which combines the advantages of the hardware-
form of a set of components which implements parts of the global first-approach and the hardware/software co-design approach.
functionality. Due to the use of formal description methods, it is
possible to find different alternatives to the implementation of
these components. The next step is a process called hardware/soft-
3 Emulation Based Methodology
ware partitioning. The functional components found in step one
can be implemented either in hardware or in software. The goal of Analyzing the hardware-first approach we have documented
the partitioning process is an evaluation of these hardware/soft- major advantage to this method. Developers using this design
ware alternatives. Depending on the properties of the functional method focus on developing a prototype as soon as possible. This
parts, like time complexity of algorithms, the partitioning process strategy complies with the major time-to-market constraints of to-
tries to find the best of these alternatives. This evaluation process day’s high tech industry. To reduce the risk of design faults and
is based on different conditions, such as metric functions like com- cost intensive redesigns, system designers often use well known
plexity or the costs of implementation. After a set of best alterna- components instead of newly available technologies.
tives is found, the next step is the implementation of the
functional specification
components. The last step is system integration. System integra- library
tion puts all hardware and software components together and eval-
initial partitioning and preselection
uates if this composition complies with the system specification,
done in step one. If not, the hardware/software partitioning process
starts again. An essential goal of today’s research is to find and op- 6WDJH2QH
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timize algorithms for the evaluation of a partitioning. Due to the
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Nevertheless, there are some basic restrictions which apply to the D

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use of this methodology: no

yes yes
• Insufficient knowledge: As described in this section, hard- System Integration
ware/software codesign is based on the formal description of
the system and a decomposition of its functionality. In order System Test

to commit to real applications, the system developer has to

use available components, like IP-cores. Using this approach,
it is necessary to describe the behavior and the attributes of Figure 1: Emulation Based Methodology
these components completely. Due to the blackbox nature of
IP-cores, this is not possible in all cases. Our design methodology tries to benefit from the advantages
• Degrees of freedom: Another of the building blocks of hard- of rapid system design, without the disadvantages of the restric-
ware/software codesign is the unrestricted substitution of tions described in the previous section. The methodology can be
hardware components by software components and vice described as a two-stage process:
versa. For real applications, there are only a few degrees of • Stage One - System design by evaluation: The basic goal of
freedom in regards to the microcontroller, but for ASIC or IP- this stage is the evaluation of components that can be used in
core components, there is a much greater degree of free- the system design. In contrast to the classical hardware-first
dom.This is due to the fact that there are many more IP-cores approach, this procedure is not restricted to known or already
than microcontrollers which can be used for dedicated appli- used hardware or software components. All potentially avail-
cations, available. able components will be analyzed using criteria like function-
Due to the limitations that have been mentioned, the hardware- ality, technological complexity, or testability. The source of
software co-design approach is not suitable for some design the criteria used can be data sheets, manuals, etc. The result of
projects, like very complex systems used in automotive, aeroplane this stage is a set of components for potential use, together
or space technologies. with a ranking of them.
• Stage Two: Validation by Emulation: Although stage one is
2.3 Conclusion about these state of the art based on functional and non-functional criteria, the knowl-
approaches edge and experience of the system designer still exerts a large
influence on decisions. In order to avoid fatal design errors,
Both methods have their disadvantages. The hardware first ap- stage two validates the decisions made in stage one. The basic
proach does not allow verification of the system design at an early methodology for this validation is system emulation. In con-
stage in the design flow process, the hardware/software co-design trast to other approaches like computer simulation, emulation
methodology is limited by insufficient knowledge about the inter- can check „serious“ problems, like real time behavior. It is
nal behavior of hardware- or software IP-Cores and the restricted highly essential to verify the criteria used in stage one, for
degrees of freedom in the choice of microcontroller components. example, the correctness of data sheet specifications.
Both methodologies are unsuitable for developing embedded sys-

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 Figure 1 gives an more detailed overview of our methodology. The next set of criteria for the selection of suitable components
After the specification of the system design, the developer makes is the bus interface of the microcontroller. This criteria is more im-
an initial hardware/software partitioning. The outcome is a set of portant than the other criteria shown in Figure 2, such as the ini-
hardware and software IP-Cores, the potential candidates that can tialization of a component. That is why the connection of a
be used to construct the system. The candidates can be selected component to the microcontroller is essential for estimating the fi-
from a library or another data base of information. After these in- nal costs and performance of an embedded system:
troductory steps, the first stage of our methodology follows. The The best case is complete compatibility of the busses of the mi-
evaluation and selection process focuses on a set of criteria, like crocontroller and the component which are connected each other.
testability. The output is a set of components which satisfy such Another possibility is that both bus interfaces are completely in-
special criteria in the best possible manner. Refer to [5] for a de- compatible. To connect this type of hardware component to the
tailed description of this process. After establishing the criteria, microcontroller, highly complex bridges are necessary. The appar-
the already described „validation“ stage follows. Only if a compo- ent disadvantages would be increased costs and significant com-
nent passes this „test phase“, it will be used in the final system de- munication delays between the microcontroller an the newly
sign. added component. In regards to the contents of this chapter, it is
possible to construct a ranking system to choose the most suitable
3.1 Stage One: Decision-making Criteria and component using the criteria bus-interface. The evaluation of the
Ranking other criteria, like initialization, testability, the complexity of add-
ing a component to a printed circuit board, etc., follows a analog-
The previous chapter gave a short overview of the principles of ical way. For detailed information refer to [5].
our approach. The evaluation stage which was described is based
on a process that puts together a ranking for components by focus- 3.2 Stage Two: Validation by Emulation
sing on special criteria. This chapter will explain how to define
these criterias and which ranking will be used for selecting or For the emulation of hardware and software components, we
throwing out components. have developed the SPYDER System. The basic idea of the SPY-
The most important component of an embedded system is the DER-System is to get a detailed view of the internal system beha-
microcontroller. That is why there are only a few types of control- vior of complex embedded systems based on real-time emulation.
lers available, but the choice of the microcontroller determines ba- In the past, these tools were used in different research projects pu-
sics like the system bus, power supply voltages, etc. The first stage blished in [2][3][4]. The SPYDER System currently consists of two
of our emulation-based design approach is aware of such choices, components:
as Figure 2 shows. • The SPYDER-VIRTEX-X2 Board for emulating application-
The features of the microcontroller, especially performance de- specific hardware or testing IP-cores.This board covers the
termine what will be implemented assoftware.A system which is validation of the hardware partitioning of an embedded sys-
equipped with a high performance microprocessor can implement tem design, (see Figure 1).
time-consuming functions, like MPEG-decoding software.If the • The SPYDER-CORE-P2 Board is designed for emulating soft-
microcontroller fails to complete this task, additional hardware ware components in a real-time environment. We have devel-
must be added. Due to the high costs of ASIC design, the only pos- oped a Board Support Package for the VxWorks1 RTOS. Due
sibility is to select the right components from a pool of available to the availability of this BSP, a variety of state of the art soft-
chips or IP-Cores. ware IP-cores can be tested and benchmarked.

By referring back to figure 1, you can see that the hardware and
ASIC integration functionality number of pins the software partitioning be emulated and verified at the same
time. This avoids time and cost-intensive delays between the phas-
es of hardware design and software implementation in classical
methodologies, like the hardware-first approach.
bus interface technology The next generation of boards that is currently being devel-
oped will combine these two platforms with additional internet
based configuration features. This new platform will offer devel-
opers the chance to work together in a world wide distributed en-
initializing testability vironment. Refer to section 4 for detailed information.

driver availibility
final ranking ASIC integration

Figure 2: Decision Criteria

1
VxWorks is a trademark of WindRiver systems

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 3.3 Emulation Platform Spyder-Virtex-X2 3.4 Emulation Platform SPYDER-CORE-P2

serial EEROMs 6 x 1MBit (stand-alone mode)

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created for rapid, cost-effective development of software and
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(high density hardware of the embedded system, mainly in the spheres of indus-
,&RUH connectors) trial automation, communication and automotive industries. The
board is designed to run, test and evaluate application-specific
Figure 3: Architecture of SPYDER-VIRTEX-X2 software components, as well as software developed by the sys-
tems designer company itself or third party IP-cores. Referring to
The basic component of the board is a Virtex1 FPGA with the our design methodology shown in Figure 1, SPYDER-CORE-P2
package type BG432. Therefore, FPGA chips with a range of covers the software portion of the design flow process. Figure 4
XCV300 up to XCV800 can be implemented. The architecture of shows the basic system architecture of the board. The core part is
SPYDER-VIRTEX-X2 is depicted in Figure 3. The Virtex FPGA is based on a novel 32-bit Hitachi-SH3 RISC micro controller with
closely coupled via a dedicated PCI-Interface-chip (PLX9080) to an optional on-chip Digital Signal Processing (DSP) module. To-
a PC. This feature enables both simple downloading bit images gether with 1 MB of EPROM bootspace, 4 MB SDRAM and 1 MB
onto the Virtex chip and communication between the PC and the of flash memory, the system offers all features to run state-of-the-
application operating on the Virtex FPGA via the PCI-bus, which art software components. Due to the availability of a VxWorks
provides a high performance bandwidth. The communication board support package, a wide range of RTOS based software can
makes it possible to evaluate a running application, e.g., a dedicat- be tested. SPYDER-CORE-P2 offers the most important interfaces to
ed IP-Core, before its integration into an embedded system. Using communicate with the surrounding environment. A standard serial
the PC with its entire periphery instead of a specialized micro con- interface, a CAN compliant controller and an ethernet 10Base2 /
troller makes the evaluation process much easier. Two powerful 10BaseT interface are available. This ethernet feature allows the
extension headers make it possible to connect the Virtex FPGA integration of the board in a fast ethernet-based development envi-
with further application specific hardware units. These ports are ronment, for example the Tornado Toolkit.2 Two VG96 extension
compatible with the other tools of the SPYDER-System mentioned headers can be used to integrate additional hardware components.
above via backplane, which provides different micro-controller All bus signals can be put through logic analyzer measurement by
types. A further significant feature is the ability to connect all on- connectors of mictor type.
board signals via up to nine high density connectors to a logic an- Together with SPYDER-VIRTEX or separately, SPYDER-CORE-
alyzer. These connectors provide a powerful support during the P2 can be efficiently used in increasingly wider application areas.
debugging process. An arbiter controls the local side of the PCI- The board has been carefully optimized for high performance and
bus between PLX9080 and three different download modes, which low power consumption. Supporting innovative design approach-
can be summarized as follows: es and tools, SPYDER-CORE-P2 allows development, modification
• download via PCI-bus, set Virtex in slave mode and the testing of new designs in shorter time frames, achieving
• download via external master, e.g. a micro controller-unit, set high-quality characteristics.
Virtex in slave mode
• download via serial EEPROMs, set Virtex in master mode, 4 Distributed Developing Environment:
used for stand-alone mode
SPYDER-VIRTEX-X3
Additionally, two on board 128kx32 SSRAM-devices enable The next generation of boards called SPYDER-VIRTEX-X3 is
the emulation of applications, which need a large extension mem- currently under development. This system enhances the features of
ory for, such things as graphic or large filter applications. For more the SPYDER series. The most important new feature of the architec-
information, refer to the corresponding user manual and data sheet ture is its scalability and the possibility to integrate the emulation
in [1]. system in a world-wide, internet-based, distributed environment.

1 2
Virtex is a trademark of Xilinx Inc. Tornado is a trademark of WindRiver Systems

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 4.1 Scaleability communication. The SPYDER-VIRTEX-X3 acts as a master of a
scalable environment as shown in Figure 5. Together with SPY-
In order to emulate an embedded system design, it is necessary DER-CORE or SPYDER-VIRTEX boards, the developer can use a
to test several components and their communication with each oth- powerful and flexible emulation environment for testing embed-
er at the same time. Although the SPYDER System is highly quali- ded system designs without a prototype. The configuration inter-
fied for validating hardware or IP-core components, there is a face of SPYDER-VIRTEX-X3 is based on a Hitachi SH3 CPU
limitation given by the complexity of the FPGA chip used. In prin- running the real time operating system VxWorks. Due to the avail-
ciple there are three ways to remove this barrier: ability of a TCP/IP stack, this interface can use all TCP/IP based
• Use FPGAs with a higher gate density: This solution can be protocols, for example HTTP, FTP or proprietary protocols.
used for special designs needing a fixed number of gates for Flash Memory SDRAM Ethernet
emulation. Due to increasing cost and technological and test- Flash Driver, RAM Driver, Ethernet Driver,
DOS file system DOS file system TCP/IP stack
ing problems for ballgrid chips with hundreds of pins, this
approach is not suitable as emulation environment, which
could be put into common use. Application
• Increase the ‚virtual‘ gate capacity of the FPGA by using an
approach called „run-time-reconfiguration“ (RTC). Run-time
reconfiguration is a methodology focusing to a temporal par- FPGA Driver

titioning of a hardware design. The result of this process is a FPGA

set of time-exclusive functional components. Only one of
these components will be active at the time t0. The goal of Figure 6: Software Architecture of SPYDER-
RTC is to load design parts on demand. Using RTC allows the VIRTEX-X3
implementation of designs larger than the physical gate
capacity of the FPGA, because not all parts are active at the Figure 7 shows our FTP-based interface. The major parts are a
same time. One important restriction of RTC is the necessity ftp server running on the RTOS VxWorks and a flash based DOS
of the existence of time exclusive design components. file system. Both the server and the flash drivers were developed
• design a scalable emulation system by us to offer an easy-to-use reconfiguration environment. The
software architecture is shown in Figure 6. This architecture sup-
The new generation of our emulation system uses the third plies a set of hardware designs or IP-cores. These IP-cores are
variant. Although the existing SPYDER-VIRTEX System can be available as bit images, generated by software tools from VHDL-
scaled by connecting up to five boards by a backplane, there are libraries or other file formats. These images can be selected and
some limitations regarding the configuration of the FPGAs. loaded onto the Virtex FPGA device. In Figure 6, there are basi-
scalable in size backplanes cally two sources for tapping into the design files. The first one is
86

the local file system, based on a persistent flash memory file sys-
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Xilinx Virtex FPGA 86
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Figure 7: FTP based interface

Figure 5: Basic Architecture of SPYDER-VIR-
TEX-X3
The second source is a world-wide network of external servers,
available via the ethernet interface of the board and the TCP/IP
To make the FPGAs in-system-programmable, it is necessary stack of VxWorks. The modified FTP server is a frontend for man-
to connect the boards with the PCI bus of a host PC. Due to the use aging all the sources and for integrating it in the environment of
of a PC there are restrictions in scalability (number of PCI slots). the developers host PC. Figure 7 shows the way this user interface
When dealing with automotive environments, aircraft etc., devel- works. Using a standard ftp client program, the developer can ac-
opers often have to test an embedded system without any addition- cess the local file system (background window) of the emulation
al equipment such as host PCs. They need a scalable and powerful board as well as the design files stored on his developing host PC
emulation environment that also works in stand alone mode. Con- or on an external server (highlighted window). The most important
sidering this we have decided to develop a scalable emulation plat- feature of our ftp server is the so-called „special directory“. These
form with a TCP/IP based interface for configuration and directories appear to the user as normal folders, but they are asso-

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 ciated with device drivers. By uploading a fpga image file in such 5 Results: Automotive Industries
a directory (i.e. , Spyder_I), the files are not stored on the target’s
flash file system, but will be redirected via a driver to the Virtex In the last months, we worked closely with an automotive com-
FPGA device. This feature offers the ability to reconfigure FPGAs pany developing different applications running a real-time operat-
simply by using drag and drop. Due to the use of the FTP protocol, ing System (RTOS). The company had used the hardware first
the developer can work with any host architecture he wants. method. After developing a complex prototype, the software de-
velopers started to code their applications. While the automotive
4.2 Distributed Emulation Environment team was still developing their hardware, we had started to port the
VxWorks RTOS using our SPYDER-CORE-P2 emulations system.
Due to the TCP/IP facilities of VxWorks, the emulation envi- This was possible and not difficult even without the availability of
ronment is not limited to a simple target/host development envi- the customers own hardware. Benefiting from the debugging facil-
ronment. Although the ftp interface still offers a comfortable and ities of SPYDER-CORE-P2, VxWorks was ready to run within two
flexible working environment, there are much more powerful weeks, before the hardware of our partner company was available.
ways to benefit from the internet capabilities of SPYDER-VIRTEX- Using the SPYDER emulation system, the behavior of the target’s
X3. microcontroller architecture could be analyzed in detail by con-
Due to the global structure of todays business, classical work- necting it to a standard logic analyzer. It was possible to detect
ing environments become more and more obsolete. Imagine a vir- some tricky bugs and to fix them. Because the emulation system
tual company developing and producing high-end electronic itself was tested, developers can focus on debugging their own ap-
products. There are software developing offices in the United plications, without regard for the problems of newly available pro-
States, the hardware developers are Europeans and the production totypes. To gain from the benefits of an emulation-based design
labs are located in Asia. The developer teams can work in different methodology, our partner company has decieded to use this ap-
locations, some of them develop parts of the system like ASICs, proach in the future by using the SPYDER tool set.
other engineers have to integreate all parts of an embedded system.
The challange is to enable a „distributed office“, that means offer-
ing the ability to work together in a simple fashion. Classical com-
6 Summary
munication paths like email or the world-wide web are powerful,
but sometimes restricted. These restrictions are based on the dif- The major advantages of our methodology is a parallel design
ferent know-how of the parties working together. Software devel- flow for hardware and software, rapid prototyping and the avoid-
opers have very good skills in debugging code of any kind, but ance of dangerous design risks. We have developed an emulation
they are not able to understand a complex hardware design in de- system called SPYDER to use our approach with real system de-
tail. Developing very complex systems, like an airplane or space- signs. The methodology and the SPYDER tool set are successfully
craft, each developer only knows a part of the whole design in applied in industrial OEM development projects. The basic goal of
detail. Imagine the following situation as an illustration of this our research activities is a world wide distributed development en-
point. A hardware developer team designs a high-end ASIC with vironment as introduced in section 4.2.
millions of transistors. Due to the complexity of the chip, there are
more than one team, each developing a part of the chip. The sys- References
tem designers have to integrate the ASIC in an embedded system.
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these people. To fix a bug in the IP-Core design, normally the re- TEX-X2 user manual, version 1.0, http://www.fzi.de/sim/spy-
sponsible ASIC team would have to change their design and to up- der.html, september 1999.
grade the ASIC. Of course they have to guarantee the consitence
[2] K. Weiß, T. Steckstor, C. Nitsch, W. Rosenstiel: Perfor-
of the design. Due to the complexity of such an upgrade process,
only the ASIC developers can do it. In pratice they design a new mance Analysis of Real-Time-Operation Systems by Emula-
image file for a FPGA emulating the chip and the system designers tion of an Embedded System. 10th IEEE International
have to load it onto a special FPGA to make it available on their Workshop on Rapid System Prototyping (RSP), Clearwater,
system. Unfortunately, this process needs a lot of effort in the area Florida, USA, 1999.
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ing. Features during the Emulation of a Fast Reactive Embedded
A solution which avoids such problems is provided by the in- System. ACM/SIGDA International Symposium on Field
ternet capabilities of the SYPDER-VIRTEX-X3 system. Using an Programmable Gate Arrays (FPGA), Monterey, CA, USA,
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based software frontend, it is possible to upgrade the entire hard-
ware of the system or parts of it via the internet. The IP-Core de- [4] K. Weiss, C. Oetker, I. Katchan, T. Steckstor, W. Rosenstiel:
velopers take care of the parts of the hardware they have Power Estimation Approach for SRAM-based FPGAs. Inter-
developed, they can exchange it on the emulation system national Symposium on Field Programmable Gate Arrays
without any help from the system integrators. The system (FPGA), USA 2000
developers can focus their work on the whole embedded [5] K. Weiß: Architekturentwurf und Emulation eingebetteter
system. Systeme. Ph-D. Thesis, University of Tübingen 15.Oktober
1999

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