Digital Verification Flow

Mahmoud Saeed Elbosily, Staff Verification Engineer

Mahmoud Elbosily, Confidential to ITI Students Year 2023 9/30/2023 1

SystemVerilog for Verification
+ Verification Planning
Mahmoud Saeed Elbosily, Staff Verification Engineer

Mahmoud Elbosily, Confidential to ITI Students Year 2023 9/30/2023 2

Agenda

▪ Verification Planning Introduction

▪ Design Requirements Extraction
▪ Verification Requirements Extraction
▪ Environment Architecting
▪ SystemVerilog Flow Control
▪ SystemVerilog Functions vs. Tasks

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SystemVerilog Functions vs. Tasks -01-

▪ Tasks and functions are building blocks of design and verification logic.
▪ They allow for modular and reusable development of code.
▪ They provide the ability to execute common procedures from several places in your logic.
▪ You can parameterize tasks and functions so that they can be invoked from different
places in your code with different parameters.

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SystemVerilog Functions vs. Tasks -02-

Difference between SystemVerilog functions and tasks:

▪ A function is zero time executing block, while a task may contain time-consuming statements.
▪ A function cannot enable a task, but a task can enable other tasks or functions.
▪ A non-void function returns a value, while a void function does not return a value. A task can have
outputs that can be assigned within the task, but the task itself does not return a value.
▪ A non-void function can be used in an expression as an operand, where the value of the operand is
the value returned by the function.

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SystemVerilog Functions vs. Tasks -03-

SystemVerilog functions:
▪ A function cannot have the following operators:
#, ##, @, fork join, fork join_any, wait, wait_order or expect
▪ A statements that do not block are allowed. For example, non-blocking assignments, named event trigger, and
fork join_none are allowed.
▪ A function’s primary purpose is to return a value that is to be used in an expression.
▪ May or may not take arguments.
▪ Here is the syntax in its simplest form:
. function <automatic | static> <data_type_or_implicit_or_void> function_name ( <arguments> );
. function_body
. endfunction

▪ The return data type can be explicit or void.

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SystemVerilog Functions vs. Tasks -04-

SystemVerilog functions:
function logic [63:0] add_int (int a, int b);
▪ The 1st and 2nd syntax are the same.
endfunction
▪ The function declarations default to the formal direction
“input”.
function logic [63:0] add_int;
▪ Once a direction is given, the subsequent formals default input int a;
input int b;
to the same direction. For example:
endfunction

function logic [2:0] getVal (int a, int b, output logic [2:0] x, y);

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SystemVerilog Functions vs. Tasks -05-

SystemVerilog functions:
§ In this example, “a” and “b” are inputs, “c” is inout, and “x” and “y” are outputs.
§ input is the copy value input at the beginning.
§ output is the copy value at the end of the function.
§ inout is the copy input at the beginning and output at the end.
§ Each formal argument has a data type that can be explicitly specified or inherited from the
previous argument. The default data type is “logic”.
function logic [2:0] getVal (int a, int b, inout
c, output logic [2:0] x, y);

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SystemVerilog Functions vs. Tasks -06-

Consider the following example, what’s your

expected output?

▪ Could you explain the values of “c” ?

▪ Could you explain the values of “a” and “b”?

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SystemVerilog Functions vs. Tasks -07-

Void functions:
§ Void functions do not return a value.
§ They simply execute statements within the function body.
§ For example:

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SystemVerilog Functions vs. Tasks -08-

Automatic and static functions:

▪ Automatic functions allocate unique, stacked storage for each function call.
▪ By default, functions are “static”. You must use the keyword “automatic” with function
declaration to make it automatic.
▪ Functions defined within a class are always automatic.
▪ Static means the memory is allocated once for all the variables of the function and shared
for each invocation of the function.
▪ You cannot have recursive or re-entrant routines with static functions. Automatic allows a
function to be re-entrant.
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SystemVerilog Functions vs. Tasks -09-

Consider the following example, what’s your

expected output?

▪ Could you expect the output, if it declared as static?

▪ Give an example for:
• Static function with automatic variables
• Automatic function with static variables

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SystemVerilog Functions vs. Tasks -10-

Closer look into the previous example:

▪ In our example, the re-entrant function dynamically makes multiple recursive
instantiations of itself.
▪ Each functions instance gets its “automatic” variables mapped on the stack.
▪ The more progress into the recursion, the stack grows more.
▪ When the function calls return, the computed values are collated, and a finally the last
result made available.
▪ With only static variables, each function call will store the variable values at the same
common address, thus erasing any benefit of having multiple calls (instantiations).
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SystemVerilog Functions vs. Tasks -11-

Consider the following example, what’s your

expected output?

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SystemVerilog Functions vs. Tasks -12-

SystemVerilog tasks: task <static | automatic> task_name (<task port list>);

task_body
▪ A task may/may not consume time. endtask

▪ Tasks can use blocking and non-blocking assignments.

▪ A task can enable other tasks/functions, which in turn can enable furthermore tasks.
▪ Variables declared inside a task are local to that task. They can drive global variables
external to the task.
▪ Tasks are static by default.
▪ A task is automatic by default within a “class”. Lifetime of “class” methods are always
automatic.
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SystemVerilog Functions vs. Tasks -13-

Consider the following example:

▪ What’s the expected output?
▪ Did you notice the invoking of the function?

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SystemVerilog Functions vs. Tasks -14-

Automatic and static tasks: “same as discussed in functions”

▪ Same as functions, tasks (outside a “class”) are static by default.
▪ A task may be enabled more than once concurrently. All variables of an automatic task will
be replicated on each concurrent task invocation to store state specific to that invocation.
▪ All variables of a static task will be static in that there will be a single variable
corresponding to each declared local variable in a module instance, regardless of the
number of concurrent activations of the task.

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SystemVerilog Functions vs. Tasks -15-

Consider the following examples: What’s the expected output?

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SystemVerilog Functions vs. Tasks -16-

SystemVerilog functions and tasks:

▪ SystemVerilog allows two means for passing arguments to tasks and functions: by value
or by reference.
▪ Arguments can be bound by name or by position.
▪ Task or function arguments may have default values.

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SystemVerilog Functions vs. Tasks -17-

Consider the following example:

▪ What’s the expected output?
▪ What’s the difference between:
• X = add();
• X = add(5,10);
• X = add(.a(15), .b(20));
§ What about the keyword ref in mul_by_2
function?
§ Can we execute X = add(), given that one of
the add function arguments with has no
default value?

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SystemVerilog Functions vs. Tasks -18-

Could we have a parameterized task or function?

The typical answer is YES. Let’s talk about this point when we discuss:

OOP/
SV Class
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 Thank You!

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