EEE 3103: Digital Electronics I

Chapter-9: Counters
Reference: Digital Fundamentals by Thomas L. Floyd [11th Edition]

Prepared by-
Baizeed Ahmed Bhuiyan
Lecturer (Grade-I)
Department of Electrical and Electronic Engineering
Ahsanullah University of Science and Technology
❑COUNTERS:
Flip-flops can be connected together to perform counting operations. Such a group of
flip-flops is a counter, which is a type of finite state machine. The number of flip-flops
used and the way in which they are connected determine the number of states (called
the modulus) and also the specific sequence of states that the counter goes through
during each complete cycle.

Counters are classified into two broad categories according to the way they are
clocked: asynchronous and synchronous.

➢ In asynchronous counters, commonly called ripple counters, the first flip-flop is

clocked by the external clock pulse and then each successive flip-flop is clocked by
the output of the preceding flip-flop.

➢ In synchronous counters, the clock input is connected to all of the flip-flops so that
they are clocked simultaneously.
 COUNTERS

Asynchronous
Synchronous
(Ripple)

Up/Down Counter (Counts in

Up Counter (Counts Down Counter (Counts
Ascending or Descending order
in Ascending order) in Descending order) depending on a control input)

T Flip-flops or Toggle Mode of J-K Flip-flops can be used to conveniently design

counters. However, D Flip-flops can also be used for counter design.
❑2-BIT ASYNCHORNOUS UP COUNTER
(Frequency Division by 2 Circuit):
No. of Bits=No. of Flip-flops required= n= 2
Total no. of counts/states= 2n= 22=4=No. of pulses required for completing a count
Minimum Count= 0; Maximum Count= 2n-1=22-1=3
❑4-BIT ASYNCHORNOUS UP COUNTER:
No. of Bits=No. of Flip-flops required= n= 4
Total no. of counts/states= 2n= 24=16=No. of pulses required for completing a count
Minimum Count= 0; Maximum Count= 2n-1=24-1=15
CLK QD QC QB QA CLK QD QC QB QA CLK QD QC QB QA
0 0 0 0 0 8 (↓) 1 0 0 0 16 (↓) 0 0 0 0
1 (↓) 0 0 0 1 9 (↓) 1 0 0 1
2 (↓) 0 0 1 0 10 (↓) 1 0 1 0
3 (↓) 0 0 1 1 11 (↓) 1 0 1 1
4 (↓) 0 1 0 0 12 (↓) 1 1 0 0
5 (↓) 0 1 0 1 13 (↓) 1 1 0 1
6 (↓) 0 1 1 0 14 (↓) 1 1 1 0
7 (↓) 0 1 1 1 15 (↓) 1 1 1 1
❑MODULUS-N (MOD-N) RIPPLE COUNTERS:
The modulus of a counter is the number of unique states through which the counter
will sequence. The maximum possible number of states (maximum modulus) of a
counter is 2n, where n is the number of flip-flops in the counter. Counters can be
designed to have a number of states in their sequence that is less than the maximum of
2n. This type of sequence is called a truncated sequence.

In a MOD-N counter, N is the total no. of unique states/counts. 2-bit, 3-bit, 4-bit
counters can be termed as MOD-4, MOD-8, and MOD-16 counters respectively. But
how can we design a MOD-6 up counter? Let us observe the following information.

• No. of Flip-flops required= 𝒍𝒐𝒈𝟐 (𝑵)= 𝒍𝒐𝒈𝟐 (𝟔)= 2.585= 3 (Round up for fractions)
• Total no. of counts/states= N= 6=No. of pulses required for completing a count
• Minimum Count= 0; Maximum Count= N-1=6-1=5
Designing a Counter using 3 flip-flops usually counts from the sequence 000 to 111. But we need to
stop the count sequence at 101 here. When 110 sequence occurs, it should forcefully be made 000. To force
any output, we can use the Asynchronous PRESET (PRE) and CLEAR (CLR) inputs discussed earlier. For
this particular case, we will need to activate CLEAR inputs of the flipflops only when the sequence 110
occurs, otherwise these will remain inactive. Also, the preset inputs will remain inactive. These inputs
are also known as Overriding Inputs. These inputs are Active Low.

CLK QC QB QA
0 0 0 0
1 (↓) 0 0 1
2 (↓) 0 1 0
3 (↓) 0 1 1
4 (↓) 1 0 0
5 (↓) 1 0 1
6 (↓) 0 0 0
7 (↓) 0 0 1
❑MOD-10 (BCD) RIPPLE COUNTER:
• No. of Flip-flops required= 𝒍𝒐𝒈𝟐 (𝑵)= 𝒍𝒐𝒈𝟐 (𝟏𝟎)= 3.322= 4 (Round up for fractions)
• Total no. of counts/states= N= 10=No. of pulses required for completing a count
• Minimum Count= 0; Maximum Count= N-1=10-1=9
Notice that only QB and QD are connected to the NAND gate inputs. This arrangement is an
example of partial decoding, in which the two unique states (QB = 1 and QD = 1) are sufficient
to decode the count of ten because none of the other states (zero through nine) have both QB
and QD HIGH at the same time. When the counter goes into count ten (1010), the decoding
gate output goes LOW and asynchronously resets (clears) all the flip-flops.
❑3-BIT ASYNCHORNOUS DOWN COUNTER:
Previously, we have seen that, for asynchronous negative edge-triggered up counter,
if outputs are taken from the complements, it can function as down counter. Here is
another approach for designing an asynchronous down counter.

For negative-edge triggering:

➢ Clock connection from previous Q, outputs taken from Q→ Up Counting
➢ Clock connection from previous Q, outputs taken from 𝑸ഥ → Down Counting
ഥ , outputs taken from Q→ Down Counting (Used here)
➢ Clock connection from previous 𝑸
For positive-edge triggering:
➢ Clock connection from previous Q, outputs taken from Q→ Down Counting
ഥ , outputs taken from Q→ Up Counting
➢ Clock connection from previous 𝑸
❑3-BIT ASYNCHORNOUS UP/DOWN COUNTER:
A control bit, suppose M, controls Up or Down Counting operation.
A combinational circuit is place between the flip-flops to implement this control.
Suppose, when M=0, the counter operates as Up Counter, and M=1 makes it a down
counter.

M Q ഥ
𝑸 Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
❑ Synchronous Counters
The term synchronous refers to events that have a fixed time relationship with each
other. A synchronous counter is one in which all the flip-flops in the counter are
clocked at the same time by a common clock pulse. J-K flip-flops or T Flip-flops are
used to illustrate most synchronous counters. D flip-flops can also be used but
generally require more logic because of having no direct toggle or no-change states.

Steps for Design: Let us Design a 3-bit Synchronous Up Counter.

➢ Step-1: Determine the type and no. of Flip-flops required. No. of flip-flops is the
same as the no. of bits, so for this case, 3 Flip-flops are required. Also, we can use
any flip-flop, but for simplicity, we are choosing T Flip-flops.
➢ Step-2: Draw the State Diagram. If necessary, construct the Excitation table of the
chosen flip-flop too.
➢ Step-3: Construct the State Table and determine the inputs to the flip-flops as per
the excitation table.
➢ Step-4: Derive SOP expressions for each flip-flop from the table by solving K-map.
➢ Step-5: Illustrate the circuit.
➢Step-2:
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table of T Flip-flop

State Diagram of 3-bit Binary Up Counter

➢Step-3:
Present
Next States Excitation
States
QC QB QA
QC QB QA TC TB TA
(t+1) (t+1) (t+1)
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
➢Step-4:
➢Step-5:

Design Yourself:
➢ 3-bit Synchronous Down Counter
➢ 4-bit Synchronous Up Counter
➢ 4-bit Synchronous Down Counter
➢ Step-1: The state diagram is as shown. Although there are only four states, a 3-bit counter is
required to implement this sequence because the maximum binary count is seven. Since the
required sequence does not include all the possible binary states, the invalid states (0, 3, 4,
and 6) can be treated as don’t-cares in the design. However, if the counter should
erroneously get into an invalid state, you must make sure that it goes back to a valid state.
(We are not using D flip-flops as mentioned in the question for simplicity, but the design
can well be done using D flip-flops.) So, three T flip-flops are required for the design.
 ➢Step-3: Present States Next States Excitation
QC QB QA
QC QB QA TC TB TA
(t+1) (t+1) (t+1)
0 0 1 0 1 0 0 1 1
0 1 0 1 0 1 1 1 1
1 0 1 1 1 1 0 1 0
1 1 1 0 0 1 1 1 0
➢Step-4:
➢Step-5:

Synchronous Counter with irregular Binary Count sequence

❑ Design a 3-bit Synchronous Up/Down Counter.

A control bit, suppose M, controls Up or Down Counting operation.

Suppose, when M=0, the counter operates as Up Counter, and M=1 makes it a
down counter.

➢ Step-1: Determine the type and no. of Flip-flops required. No. of flip-flops is
the same as the no. of bits, so for this case, 3 Flip-flops are required. Also, we
can use any flip-flop, but for simplicity, we are choosing T Flip-flops.
➢ Step-2: Draw the State Diagram. If necessary, construct the Excitation table of
the chosen flip-flop too.
➢ Step-3: Construct the State Table including the control bit and determine the
inputs to the flip-flops as per the excitation table.
➢ Step-4: Derive SOP expressions for each flip-flop from the table by solving K-
map.
➢ Step-5: Illustrate the circuit.
➢Step-2:
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table of T Flip-flop

State Diagram of 3-bit Binary Up/Down Counter

➢Step-3:
UP COUNT (M=0) DOWN COUNT (M=1)
Present States Next States Excitation Present States Next States Excitation
QC QB QA QC QB QA
M QC QB QA TC TB TA M QC QB QA TC TB TA
(t+1) (t+1) (t+1) (t+1) (t+1) (t+1)
0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1
0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1
0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1
0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 0 0 0 1
0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1
0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 0 0 1
0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1
0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1
➢Step-4:
 ➢Step-5:

3-bit Synchronous Binary Up/Down Counter

➢ See Example 9-5 from Digital Fundamentals by Thomas L. Floyd (11th Edition)
 STATE MACHINE DESIGN
Example-1
Assume that the MOD-8 counter is in the 101 state. What will be the state
(count) after 13 pulses have been applied?
Example-1 (Contd.)

✓Locate the 101 state on the state transition diagram. Proceed

around the state diagram through eight state changes, and
you should be back in the 101 state. Now continue through
five more state changes (for a total of 13), and you should end
up in the 010 state.

✓Notice that because this is a MOD-8 counter with eight states,

it takes eight state transitions to make one complete excursion
around the diagram back to the starting state.
Example-2
• Consider a counter circuit that contains a six FFs wired in the
arrangement (Q5, Q4,Q3,Q2,Q1,Q0).
a) Determine the counter’s MOD number
b) Determine the frequency at the output of the last FF(Q5) when the
input clock frequency is 1 MHz.
c) What is the range of counting for this counter
d) Assume a starting state (count) of 000000, what will be the counter’s
state after 129 pulses?
Example-2 (Contd.)
• MOD number = 26 = 64.
• The frequency at the last FF will equal the input clock frequency divided by
the MOD number. That is,
• f(at Q5) =1 MHz/64 = 15.625 kHz
• The counter will count from 0000002 to 1111112 (0 to 6310) for a total of 64
states.
• Note that the number of states is the same as the MOD number.
• Because this is a MOD-64 counter, every 64 clock pulses will bring the
counter back to its starting state. Therefore, after 128 pulses, the count is
back to 000000. The 129th pulse brings the counter to the 000001 counter.