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Chapter 1 MIC Summarize

The Intel 8086 is a 16-bit microprocessor released in 1978, featuring a segmented memory architecture and supporting various processor modes. It includes internal registers and a comprehensive instruction set, with memory divided into 16 logical segments. The document details the microprocessor's signal descriptions, operating modes, register organization, memory segmentation, and address generation methods.

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18 views4 pages

Chapter 1 MIC Summarize

The Intel 8086 is a 16-bit microprocessor released in 1978, featuring a segmented memory architecture and supporting various processor modes. It includes internal registers and a comprehensive instruction set, with memory divided into 16 logical segments. The document details the microprocessor's signal descriptions, operating modes, register organization, memory segmentation, and address generation methods.

Uploaded by

arsalaanshaikh2007
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 1: 8086 16-Bit Micro Processor

o The Intel 8086 is a 16-bit microprocessor released in 1978,


featuring a 16-bit data bus and a 20-bit address bus providing
access to 1 MB of memory.

o It employs a segmented memory architecture and supports


multiple processor modes including real, protected, and virtual
modes.

o The 8086 includes internal registers like the Accumulator,


Base, Count, and Data registers, and has a comprehensive
instruction set.

Signal Description of 8086 Microprocessor

o The 8086 microprocessor is a 16-bit CPU available in 5, 8, and


10MHz clock rates, packaged in a 40-pin package.

o It operates in single or multiprocessor configurations and its


signals can be categorized into common, minimum mode, and
maximum mode functions.

o AD15-AD0 are time multiplexed memory I/O address and data


lines active during T1-T4 clock states, while A19/S6, A18/S5,
A17/S4, A16/S3 are time multiplexed address and status lines.

Signal Description Continued

o Status lines S4 and S3 indicate the segment register used for


memory accesses, while S6 is always low.

o The RD (Read) signal, when low, indicates a memory or I/O


read operation, and the READY signal acknowledges
completion of data transfer from slow devices.

o INTR is a level-triggered interrupt request, TEST input is


examined by a 'WAIT' instruction, NMI is a non-maskable
interrupt, and RESET terminates current activity and starts
execution from FFFF0H.

Clock Input and Operating Modes

o The CLK input provides timing for processor operation, with


frequencies ranging from 5MHz to 10MHz, and VCC provides
+5V power.

o The MN/MX pin determines whether the processor operates in


minimum (single processor) or maximum (multiprocessor)
mode.
o In minimum mode, M/IO indicates memory or I/O operation,
INTA acknowledges interrupts, and ALE indicates valid address
availability.

Minimum Mode Operation

o DT/R decides data flow direction, DEN enables transceivers for


data separation, and HOLD/HLDA manage bus access requests
from other masters.

o S2, S1, S0 are status lines reflecting the operation type, while
in maximum mode LOCK prevents other bus masters from
gaining bus control during critical instructions.

o QS1, QS0 provide information about the code-prefetch queue


status.

Register Organization

o The 8086 microprocessor includes general-purpose registers


like AX (Accumulator), BX (Base), CX (Count), and DX (Data)
registers, each serving specific functions.

o The AX register can be used for I/O operations and string


manipulation, BX as a base register, CX as a counter in string
and loop instructions, and DX for I/O operations and in
multiply/divide instructions.

o The Flag Register holds status flags reflecting CPU status and
results of arithmetic operations.

Segment Registers

o The 1MB memory is divided into 16 logical segments, each


64KB, addressed by segment registers: Code Segment (CS),
Stack Segment (SS), Data Segment (DS), and Extra Segment
(ES).

o CS holds the address of the code segment, SS holds the


address of the stack segment, DS holds the address of the
data segment, and ES holds the address of an extra data
segment.

o Pointers like IP, BP, SP contain offsets within the code, data,
and stack segments, while SI and DI are used for indexed and
indirect addressing in string manipulation.

Flag Register and Control Pins


o The Flag Register contains conditional/status flags (Carry,
Parity, Auxiliary Carry, Zero, Sign, Overflow) and control flags
(Trap, Interrupt, Direction).

o Status flags reflect the result of ALU operations while control


flags manage processor modes and interrupt handling.

o The READY pin acknowledges data transfer completion from


slow devices, and the INTR pin is a level-triggered interrupt
request input.

BHE, A0 Pins and Single Stepping

o BHE (Bus High Enable) indicates data transfer on data bus D8-
D15, while A0 is analogous for the lower byte D0-D7.

o Setting the Trap Flag (TF) enables single-step mode,


generating an internal interrupt after each instruction, useful
for debugging.

o Instructions to set the trap flag involve pushing flags onto the
stack, modifying the flag register, and restoring it.

Pipelining in 8086

o Pipelining involves fetching the next instruction while the


current instruction is being executed, made possible by using
a queue.

o The BIU (Bus Interface Unit) fills the queue and restarts when
at least two locations are vacant, improving processor
efficiency and execution speed.

o Pipelining reduces EU waiting time and speeds up processing


by fetching instructions ahead of time.

Memory Segmentation

o Memory segmentation logically divides main memory into


segments, each with its base address, enhancing execution
speed.

o In 8086, physical memory is divided into Data, Code, Stack,


and Extra segments, each 64KB and addressed by CS, DS, ES,
or SS.

o The segment register holds the starting address, with a 16-bit


offset (0000 to FFFFH) specifying location within the segment,
allowing up to 16 segments in the 1MB memory.
Advantages of Segmentation

o Segmentation allows addressing 1 MB of physical memory by


dividing it into 16 segments of 64 KB each.

o It provides separate spaces for Data, Code, Stack, and an


Extra Data segment, with segment addresses assigned from
0000H to F000H and offset values from 00000H to FFFFFH.

o Segmentation increases execution speed by enabling the


processor to fetch and execute data from memory more
efficiently.

Logical, Effective, and Physical Addresses

o A logical address is generated by the CPU based on the


program, while an effective address is the operand's offset
from the segment's beginning.

o Physical address generation involves appending four 0 bits to


the 16-bit base address from the segment register and adding
the 16-bit offset from a base/pointer or index register.

o Example: If CS = 1000H and IP = 1100H, the physical address


is calculated as (CS * 10H) + IP = 11100H.

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