After reading this post, you’ll be able to:

1. Write the Verilog code for a 4:1 MUX in all layers of abstraction (modeling styles)
2. Generate the RTL schematic for the 4:1 MUX and simulate the design code usin

What is a multiplexer?
A multiplexer is a data selector device that selects one input from several input lines, depend
and yields one single output.

A multiplexer of 2n inputs has n select lines, are used to select which input line to send to t
in the multiplexer, no matter what’s its configuration.
These devices are used extensively in the areas where the multiple data can be transferred
communication systems and bus architecture hardware. Visit this post for a crystal clear exp
 Contents
Gate level modeling
Logic circuit
Verilog code for 4×1 multiplexer using gate-level modeling
RTL Schematic
Data flow modeling
Verilog code for 4×1 multiplexer using data flow modeling
RTL Schematic
Behavioral modeling
Truth table
Verilog code for 4×1 multiplexer using behavioral modeling
RTL Schematic
Structural modeling
Logic circuit
Verilog code for 4×1 multiplexer using structural modeling
RTL Schematic
Testbench for 4×1 mux using Verilog
Simulation Waveforms

Gate level modeling

The gate-level abstraction is the lowest level of modeling. The switch level model is also a lo
common. The gate-level modeling style uses the built-in basic logic gates predefined in Veril
diagram of the system since the only requirement is to know the layout of the particular logic
Verilog code for 4×1 multiplexer using gate-level model
To start with the design code, as expected, we’ll declare the module first. The port-list will co
level modeling. This is because the built-in logic gates are designed such that the output is
other input variables or signals.

module m41(out, a, b, c, d, s0, s1);

Now since the nature or behavior of the circuit in the gate – level isn’t concerned, there is no
variable.

output out;
input a, b, c, d, s0, s1;

The intermediate signals are declared as wires. Note that the intermediate signals are those
Example: signals that are emerging from the NOT gate.

wire sobar, s1bar, T1, T2, T3, T4;

Time for us to write for the logic gates. Separate the list for a particular gate by appropriate b
same logic gate. Here’s how you would do it for the two NOT gates.

not (s0bar, s0), (s1bar, s1);

 module m41(out, a, b, c, d, s0, s1);

output out;
input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;

not (s0bar, s0), (s1bar, s1);

and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar),
or(out, T1, T2, T3, T4);

endmodule

RTL Schematic
This hardware schematic is the RTL design of the circuit. Notice the resemblance between th
picture. It is clear that the gate-level modeling will give the exact involved hardware in the cir

RTL schematic Gate-level modeling

Data flow modeling

Using the assign statement to express the logical expression of the circuit. A ternary operat
logic. This operator works similar to that of C programming language.

assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

This shows that if s1 is high, the (s0 ? d : c) block will be executed, else (s0 ? b : a) will be ex
will get transferred to the out variable, depending on the s1 select line, else c OR a will be th
Thus, the final code for the 4:1 multiplexer using data-flow modeling is given below.

module m41 ( input a,

input b,
input c,
input d,
input s0, s1,
output out);

assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

endmodule

RTL Schematic
You can observe how the RTL of 4:1 MUX in dataflow is different from the gate-level modelin
individual 2:1 multiplexers, connected by the two select lines s0 and s1.
 Truth table of 4×1 Mux

Verilog code for 4×1 multiplexer using behavioral mode

To start with the behavioral style of coding, we first need to declare the name of the module a
will further contain the input and output variables. Point to be noted here; we are supposed to
declared variable also since it will account for the behavior of the input and output signals.
s0 s1 select lines will be vector quantities, and vector net entities are declared as wire. The

module m41 ( a, b, c, d, s0, s1, out);

input wire a, b, c, d;
input wire s0, s1;
output reg out;

Next comes the initial and always. In behavioral modeling, there are two main statement
Verilog.
One is the initial statement, which is executed only once during the simulation; another o
be executed every time its sensitivity list gets triggered.
If you carefully look at the equation, the output is explicitly dependent on the input variables.
the always statement, followed by begin...end block.

always @ (a or b or c or d or s0 or s1)
begin
...
end

In most of the cases, the input variables are present in the sensitivity list. Another way of exp
 case (case_expression)
case_item1: procedural_expression;
case_item2: begin
procedural_statements;
end
....
default: expression;
endcase

The expression for case_expression is the OR (symbol |) operation between select lines. An
the case statement for the first row.

2'b00 : out <= a;

The above line shows that when select line s0 and s1 is 00, a input is transferred to the outp
rows of cases.
The final code for 4×1 MUX in behavioral modeling is as follows:

module m41 ( a, b, c, d, s0, s1, out);

input wire a, b, c, d;
input wire s0, s1;
output reg out;

always @ (a or b or c or d or s0, s1)

begin

case (s0 | s1)

2'b00 : out <= a;
2'b01 : out <= b;
2'b10 : out <= c;
 RTL schematic behavioral modeling

Structural modeling
In structural modeling, we describe the physical structure of a digital system. It is implemente
diagram. It gives us the internal hardware involved in the system.
There’s one thing that should be noted over here. Gate-level modeling is different from struct
use the predefined built-in logical gates. In contrast, in structural-level, we create a separate
with its logical expression assigned to that module.

Logic circuit
The end of the module is marked by endmodule keyword.

endmodule

Repeat the above for the rest of the gates=>

NOT gate:=

module not_gate(output f, input e);

assign e = ~ f;
endmodule

OR gate:=

module or_gate(output l, input m, n, o, p);

assign l = m | n | o | p;
endmodule

You may notice the names of the input and output variables are different from each of the mo
signals during the simulation of the circuit.
Time for us to combine these three gates to form a 4:1 MUX. This is called the module ins
of the module (defined and declared above) and write the name of the instance of your choic
signals, followed by the input ones.

and_gate u3(T1, a, s0bar, s1bar);

Here, the module used: and_gate

Name of the instance: u3
Output variable: T1 (which is an intermediate signal defined as a wire)
Input variable: a, s0bar, s1bar

Repeat the same for the rest of the instances.

 module and_gate(output a, input b, c, d);
assign a = b & c & d;
endmodule

module not_gate(output f, input e);

assign e = ~ f;
endmodule

module or_gate(output l, input m, n, o, p);

assign l = m | n | o | p;
endmodule

module m41(out, a, b, c, d, s0, s1);

output out;
input a, b, c, d, s0, s1;
wire s0bar, s1bar, T1, T2, T3;
not_gate u1(s1bar, s1);
not_gate u2(s0bar, s0);
and_gate u3(T1, a, s0bar, s1bar);
and_gate u4(T2, b, s0, s1bar);
and_gate u5(T3, c, s0bar, s1);
and_gate u6(T4, d, s0, s1);
or_gate u7(out, T1, T2, T3, T4);
endmodule

RTL Schematic
You can see each instantiate represents a particular functionality, comprising different logic g
Name of the module instance: name

module top;

wire out;
reg a;
reg b;
reg c;
reg d;
reg s0, s1;

m41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1))

initial
begin

a=1'b0; b=1'b0; c=1'b0; d=1'b0;

s0=1'b0; s1=1'b0;
#500 $finish;

end

always #40 a=~a;

always #20 b=~b;
always #10 c=~c;
always #5 d=~d;
always #80 s0=~s0;
always #160 s1=~s1;

always@(a or b or c or d or s0 or s1)
$monitor("At time = %t, Output = %d", $time, out);

endmodule;