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Switching Circuits and Logic Design (CS21202)

Module 9
Synthesis and Minimization of Finite State Machines

Prof. Indranil Sengupta

Dr. Monosij Maitra

Department of Computer Science and Engineering

IIT Kharagpur

Introduction

• Combinational and Sequential Circuits

• In a combinational circuit, the outputs depend only on the applied input
values and not on the past history.
• In a sequential circuit, the outputs depend not only on the applied input
values but also on the internal state.
• The internal states also change with time.
• The number of states is finite, and hence a sequential circuit is also referred to as a Finite
State Machine (FSM).
• Most of the practical circuits are sequential in nature.

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How are the States Stored and Changed?

• In a sequential circuit, we need some mechanism to store the internal

states.
• We use flip-flops or latches to store the internal states.
• If we use k flip-flops, there can be a maximum of 2k internal states.
• Depending upon the way the states change, sequential circuits can be
categorized into two types:
a) Synchronous: The states change in synchronism with a clock pulse.
b) Asynchronous: There is no clock pulse for synchronism; all state changes
occur depending on the delays of the circuit elements (e.g. gates).
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Finite State Machine (FSM)

• A FSM can be represented either in the form of a state table or in the

form of a state transition diagram.
• Variations exist, e.g. Algorithmic State Machine (ASM) chart.
• Example:
• A circuit to detect 3 or more 1’s in a serial bit stream.
• The bits are applied serially in synchronism with a clock.
• The output will become 1 whenever it detects 3 or more consecutive 1’s in
the stream. X
Z
clk

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State Table State Transition Diagram

Reset PS Input NS Output 0/0
1 - - A 0 0/0
0 A 0 A 0 A B
0 A 1 B 0 1/0
0 B 0 A 0
Reset
0/0 1/0
0 B 1 C 0
0 C 0 A 0 0/0
0 C 1 D 1
0 D 0 A 0 D C
1/1
0 D 1 D 1
1/1
A is the starting
state
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More Formal Way to Write State Table

0/0
0/0
A B PS NS, Z
1/0 RX = 00 RX = 01 RX = 10 RX = 11
Reset
A A,0 B,0 A,0 A,0
0/0 1/0
B A,0 C,0 A,0 A,0
0/0 C A,0 D,1 A,0 A,0
D A,0 D,1 A,0 A,0
D C
1/1 R: Reset
1/1 X: Input

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Mealy and Moore FSM Types

• A deterministic FSM can be mathematically defined as a 5-tuple
M = (Σ, Γ, S, s0, δ, λ)
where Σ is the set of input combinations, Γ is the set of output combinations, S is a
finite set of states, s0 ε S is the initial state, δ is the state-transition function, and λ is
the output function.
• Here, δ : S x Σ à S
• Present state (PS) and present input determines the next state (NS).
• For Mealy machine, λ : S x Σ à Γ (output depends on state + inputs)
• For Moore machine, λ : S à Γ (output depends only on the state)

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Pictorial Depiction

PI NS NS Output Mealy
F/F PS PO
Logic Logic Machine

PI NS NS PS Output Moore
F/F PO
Logic Logic Machine

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Model of Synchronous Sequential Machines

X1 Z1 Input variables X = {X1, X2, …, Xn}
Xn Combinational Zm Output variables Z = {Z1, Z2, …, Zm}
Logic State variables Y = {y1, y2, …, yk}
Input alphabet Σ :: set of 2n input patterns
y1 Y1 Output alphabet Γ :: set of 2m output patterns
y2 Y2 States S :: set of 2k k-tuples
Present State :: {y1, y2, …, yk}
yk Yk Next State :: {Y1, Y2, …, Yk}
Memory When clock comes, Next State gets copied to Present State.
elements

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Synthesis of Synchronous Sequential Circuits

1. From a description of the problem, form a state diagram or state table.

2. Check whether the table contains any redundant states; if so, remove them.
• To be discussed later.
3. Select a state assignment and determine the type of memory elements.
• We can choose any type of memory elements (flip-flops) to maintain states.
• Final circuit complexity shall depend on this selection.
4. Derive transition and output tables.
5. Derive the excitation table, and obtain excitation and output functions.
6. Minimize the functions, and obtain the circuit diagram.

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The Overall Flow Diagram

Problem Form state diagram / Identify and eliminate State

Description state table redundant states Assignment

Derive excitation table.

Obtain excitation and Derive transition and Select type of memory
output functions output tables elements

Minimize; and draw the

final circuit diagram

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State Transition Diagram and State Table

• A state transition diagram specifies the different states of a FSM, the

conditions under which state changes occur, and the corresponding
outputs.
• States are denoted as circles, and labeled with unique symbols.
• Transitions are represented as directed arrows between pair of states.
• Each transition is labeled by α/β, where α denotes an input combination and β
denotes an output combination.
• A state table is an alternate depiction of the state transition diagram.
• For every value of the present state, it specifies the next state and the output for
every input combination.

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Example 1
• There are three lamps, RED, GREEN and YELLOW, that should glow cyclically with
a fixed time interval (say, 1 second).
• Some observations:
• The FSM will have three states, corresponding to the glowing state of the lamps.
• The input set is null; state transition will occur whenever clock signal comes.
• This is a Moore Machine, since the lamp that will glow only depends on the state and not on
the inputs (here null).

φ/010 RED φ/100

RED
clock GREEN φ/001
YELLOW GREEN YELLOW

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PS NS, Z
RED GREEN, 010
φ/010 RED φ/100
GREEN YELLOW, 001
φ/001 YELLOW RED, 100
GREEN YELLOW

State Table
State Transition Diagram

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Example 2
• Design of a serial parity detector.
• A continuous stream of bits is fed to a circuit in synchronism with a clock. The circuit will be
generating a bit stream as output, where a 0 will indicate “even number of 1’s seen so far”
and a 1 will indicate “odd number of 1’s seen so far”.
• This is also a Moore Machine.

0/0 0/1
1/1
X
Z EVEN ODD
clk
Initial 1/0
state

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NS, Z
PS
0/0 0/1 X=0 X=1
1/1
EVEN EVEN, 0 ODD, 1
EVEN ODD ODD ODD, 1 EVEN, 0
1/0
State Transition Diagram State Table

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Example 3

• Design of a sequence detector.

• A circuit accepts a serial bit stream “X” as input and produces a serial bit stream “Z” as
output.
• Whenever the bit pattern “0110” appears in the input stream, it outputs Z = 1; at all other
times, Z = 0.
• Overlapping occurrences of the pattern are also detected.
• This is a Mealy Machine.
• Example: x :- 0 1 0 1 0 1 1 0 1 1 0 0 1 0 1 1 0 1 1 1 0
z :- 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0

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X The input bits “X” are applied in

Z
clock synchronism with the clock.

reset
1/0
1/0 0/0
0/0 1/0 1/0
S0 S1 S2 S3

0/0
reset 0/1

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Example 4
• A 2-bit serial adder which takes two serial bit streams X1 and X2 as inputs, and
generates a serial bit stream Z as output.

00/0 01/0
01/1 10/0
10/1 11/0 11/1
X1
X2 Z A B
clk 00/1

The state represents the carry; A means carry

is 0, B means carry is 1.

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01/0 NS, Z
00/0
10/0 PS
01/1 X = 00 X = 01 X = 10 X = 11
10/1 11/0 11/1
A A, 0 A, 1 A, 1 B, 0
A B
B A, 1 B, 0 B, 0 B, 1
00/1
State Transition Diagram State Table

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Example 5
• A 3-bit binary counter that counts in the sequence 000, 001, 010, 011, 100, 101,
110, 111, and then back again to 000.
PS NS, Z
φ/000
S0 S7 S0 S1, 001
φ/001 φ/111 S1 S2, 010

S1 S6 S2 S3, 011
φ/010 φ/110 S3 S4, 100

S2 S5 S4 S5, 101
φ/011 φ/101 S5 S6, 110
S6 S7, 111
S3 S4
φ/100 S7 S0, 000
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Example 6
• A 4-bit counter that counts in the sequence 0000, 0011, 0110, 1100, 1001, 1010,
and then back again to 0000. If the counter starts with any of the other states, it
will go to 0000 at the next clock.

S1 S2 S4 S5 S7 S8 S11 S13 S14 S15

φ/0000 …….. φ/0000

S0 S3 S6 S12 S9 S10
φ/0011 φ/0110 φ/1100 φ/1001 φ/1010

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FSM Synthesis

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FSM Synthesis

• We have seen how the state transition diagram / state table can be
constructed from the problem description.
• To construct the circuit, the following further steps are required:
• Assign unique binary code to each state: state assignment.
• Construct the transition/output table.
• Select type of memory elements: SR or JK or D or T, and construct excitation table.
• Obtain the excitation and output functions, and minimize them.
• Realize the functions using gates or any other combinational circuit modules.
• We shall illustrate the process with examples.

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Example 1: Serial Adder X1

X2 Z
clk

00/0 01/0
10/0
NS, Z
01/1 PS
10/1 11/0 11/1 X = 00 X = 01 X = 10 X = 11

A B A A, 0 A, 1 A, 1 B, 0

00/1 B A, 1 B, 0 B, 0 B, 1

State Transition Diagram State Table

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• State assignment:
• Two states, and so one bit is sufficient.
• Suppose we assign 0 for state A, and 1 for state B.

NS, Z PS NS Output Z
PS
X = 00 X = 01 X = 10 X = 11 X1X2 00 01 10 11 00 01 10 11
0 0, 0 0, 1 0, 1 1, 0 0 0 0 0 1 0 1 1 0
1 0, 1 1, 0 1, 0 1, 1 1 0 1 1 1 1 0 0 1

After state assignment Transition/output Table

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• Select memory element, and PS NS Output Z

construct excitation/output 00 01 10 11 00 01 10 11
function. 0 0 0 0 1 0 1 1 0
• Suppose we use D flip-flop.
1 0 1 1 1 1 0 0 1
Transition/output Table
X1
Z
X2 y NS (Y) Output Z
00 01 10 11 00 01 10 11
0 0 0 0 1 0 1 1 0
y Y
1 0 1 1 1 1 0 0 1
Excitation and Output Function

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X1X2 X1X2 X1
Z
y 00 01 11 10 y 00 01 11 10 X2
0 1 0 1 1
1 11 1 1 1 1 1 1
y Y
Y = X1X2 + X1y + X2y Z = X1 Å X2 Å y

y NS (Y) Output Z
00 01 10 11 00 01 10 11
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

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• Alternate design. PS NS Output Z

• Suppose we use SR flip-flop 00 01 10 11 00 01 10 11
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
X1
Z Transition/output Table
X2
Circuit changes Required value
S From To S R
y R 0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Excitation table of SR flip-flop
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• Alternate design. PS NS Output Z

• Suppose we use SR flip-flop 00 01 10 11 00 01 10 11
0 0 0 0 1 0 1 1 0

X1 1 0 1 1 1 1 0 0 1
Z
X2 Transition/output Table

y SR Output Z
S
00 01 10 11 00 01 10 11
y R
0 0X 0X 0X 10 0 1 1 0
1 01 X0 X0 X0 1 0 0 1
Excitation and Output Function

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X1X2 X1X2 X1
Z
y 00 01 11 10 y 00 01 11 10 X2
0 1 0 1 1
S
1 X X X 1 1 1 1
y R
S = X1X2’ Z = X1 Å X2 Å y
X1X2
y 00 01 11 10 y SR Output Z
0 X X X 00 01 10 11 00 01 10 11

1 1 1 0 0X 0X 0X 10 0 1 1 0
1 01 X0 X0 X0 1 0 0 1
R = X1’X2’
Excitation and Output Function
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Example 2: Sequence Detector

• Design of a sequence detector.
• A circuit accepts a serial bit stream “X” as input and produces a serial bit stream “Z” as
output.
• Whenever the bit pattern “0110” appears in the input stream, it outputs Z = 1; at all other
times, Z = 0.
• Overlapping occurrences of the pattern are also detected.
X
Z
clock
• Example: X :- 0 1 0 1 0 1 1 0 1 1 0 0 1 0 1 1 0 1 1 1 0
Z :- 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0

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1/0
1/0 0/0
0/0 1/0 1/0
S0 S1 S2 S3

0/0
0/1

PS NS, Z PS NS, Z PS NS Output Z

X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
S0 S1, 0 S0, 0 00 01, 0 00, 0 00 01 00 0 0
S1 S1, 0 S2, 0 01 01, 0 10, 0 01 01 10 0 0
S2 S1, 0 S3, 0 10 01, 0 11, 0 10 01 11 0 0
S3 S1, 1 S0, 0 11 01, 1 00, 0 11 01 00 1 0

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• Suppose we use T flip-flop.

• Two flip-flops, inputs T1 and T2.

PS NS Output Z y1y2 T1 T2 Z
X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
00 01 00 0 0 00 01 00 0 0
01 01 10 0 0 01 00 11 0 0
10 01 11 0 0 10 11 01 0 0
11 01 00 1 0 11 10 11 1 0

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y1y2 T1 T2 Z
X=0 X=1 X=0 X=1
00 01 00 0 0
01 00 11 0 0
10 11 01 0 0
11 10 11 1 0

y1y2 y1y2 y1y2

X 00 01 11 10 X 00 01 11 10 X 00 01 11 10
0 1 1 0 1 1 0 1
1 1 1 1 1 1 1 1 1

T1 = X’ y1 + X y2 T2 = X’ y2’ + y1 y2’ + X y2 Z = X’ y1 y2

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• Let us repeat the process using J-K flip-flop.

PS NS Output Z y1y2 J1 K1 J2 K2 Z
X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
00 01 00 0 0 00 0X 1X 0X 0X 0 0
01 01 10 0 0 01 0X X0 1X X1 0 0
10 01 11 0 0 10 X1 1X X0 1X 0 0
11 01 00 1 0 11 X1 X0 X1 X1 1 0

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y1y2 J1 K1 J2 K2 Z
X=0 X=1 X=0 X=1
00 0X 1X 0X 0X 0 0
01 0X X0 1X X1 0 0
10 X1 1X X0 1X 0 0
11 X1 X0 X1 X1 1 0

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