EXPERIMENT NO.

: DATE:
4X1 MUX AND DEMUX
AIM: VHDL programs for 4x1 Mux and Demux
SOFTWARE REQUIRED: ModelSim
THEORY:
4x1 Mux: A 4x1 multiplexer (MUX) is a digital circuit that selects one of four input signals
and forwards the selected input to a single output line. It has 4 data inputs, 1 output, and 2
control (or selection) lines. The control lines determine which input is connected to the
output.

1x4 Demux: A 1x4 Demux (Demultiplexer) is a digital circuit that takes a single input signal
and routes it to one of four output lines based on the values of two selection (or control)
lines. Essentially, it is the reverse of a multiplexer. The 1x4 Demux allows one data input to
be distributed to multiple output lines depending on the selection lines.
VHDL CODE WITH TESTBENCH:
4x1 Mux:
Dataflow----- Testbench-------
entity mux4x1 is entity testmux4x1 is
port (i:in bit_vector(3 downto 0); end testmux4x1 ;
s: in bit_vector(1 downto 0); architecture abc of testmux4x1 is
y: out bit); signal a: bit_vector(3 downto 0);
end mux4x1; signal b: bit_vector (1 downto 0);
architecture dataflow of mux4x1 is signal c: bit;
begin component mux4x1 is
y<=( (i(0) and(not s(1)) and (not s(0))) or port (i:in bit_vector(3 downto 0);
(i(1) and(not s(1)) and s(0)) or s: in bit_vector(1 downto 0);
(i(2) and(not s(0)) and s(1)) or y: out bit);
(i(3) and s(1) and s(0))); end component;
end dataflow; begin
il: mux4x1 port map (a,b,c);
process
begin
a<="1010"; wait for 2 ns;
b<="00" ; wait for 2 ns;
b<="01" ; wait for 2 ns;
b<="10" ; wait for 2 ns;
b<="11" ; wait for 2 ns;
end process;
end abc;

Structual----- Testbench-------

entity muxstruc is entity testmuxstruc is

port ( i: in bit_vector (3 downto 0); end testmuxstruc;
architecture abc of testmuxstruc is
s: in bit_vector(1 downto 0);
component muxstruc is
y: out bit);
port (i: in bit_vector(3 downto 0);
end muxstruc;
architecture structural of muxstruc is s: in bit_vector(1 downto 0);
component andgate y: out bit);
port ( a: in bit; end component;
signal a: bit_vector(3 downto 0);
b,c: in bit;
signal b: bit_vector (1 downto 0);
y: out bit);
signal c: bit;
end component;
begin
component orgate
tl: muxstruc port map (i=>a,s=>b,y=>c);
port ( a: in bit;
process
b,c,d: in bit;
begin
y: out bit); a<="1010"; wait for 2 ns;
end component; b<="00" ; wait for 2 ns;
component notgate b<="01" ; wait for 2 ns;
port ( a: in bit; b<="10" ; wait for 2 ns;
b<="11" ; wait for 2 ns;
end process;
end abc;
 y: out bit);
end component;
signal in0,in1,in2,in3,ns0,ns1:bit;
begin
N0: notgate port map(a=>s(0),y=>ns0);
N1: notgate port map(a=>s(1),y=>ns1);
I0: andgate port map(a=>i(0),b=>ns0 , c=> s(1) , y=>in0);
I1: andgate port map(a=>i(1),b=>s(0) , c=> ns1 , y=>in1);
I2: andgate port map(a=>i(2),b=>ns0 , c=> s(1) , y=>in2);
I3: andgate port map(a=>i(3),b=>s(0) , c=> s(1) , y=>in3);
O1: orgate port map (a=>in0,b=>in1, c=>in2, d=>in3, y=>y);
end structural;

Behavioral----- Testbench-------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity MUX4x1 is entity MUX4x1_tb is
Port (I0, I1, I2, I3 : in STD_LOGIC; end MUX4x1_tb;
S: in STD_LOGIC_VECTOR(1 downto 0); architecture Behavioral of MUX4x1_tb is
Y: out STD_LOGIC); component MUX4x1
end MUX4x1; Port (I0, I1, I2, I3 : in STD_LOGIC;
architecture Behavioral of MUX4x1 is S: in STD_LOGIC_VECTOR(1 downto
begin 0); Y: out STD_LOGIC);
process(S, I0, I1, I2, I3) end component;
begin signal I0, I1, I2, I3, Y : STD_LOGIC;
case S is signal S : STD_LOGIC_VECTOR(1 downto 0);
when "00" => Y <= I0; begin
when "01" => Y <= I1; uut: MUX4x1 port map (
when "10" => Y <= I2; I0 => I0,
when "11" => Y <= I3; I1 => I1,
when others => Y <= '0'; I2 => I2,
end case; I3 => I3,
end process; S => S,
Y => Y);
end Behavioral;
process
begin
I0 <= '0'; I1 <= '1'; I2 <= '0'; I3 <= '1';
S <= "00"; wait for 10 ns;
S <= "01"; wait for 10 ns;
S <= "10"; wait for 10 ns;
S <= "11"; wait for 10 ns;
end process;
end Behavioral;
1x4 Demux:
Testbench-------
Dataflow-----
entity demux1x4 is entity testdemux1x4 is
port (i:in bit; end testdemux1x4 ;
s: in bit_vector(1 downto 0); architecture abc of testdemux1x4 is
y: out bit_vector(3 downto 0)); signal a: bit;
end demux1x4; signal b: bit_vector (1 downto 0);
architecture dataflow of demux1x4 is signal c: bit_vector(3 downto 0);
begin component demux1x4 is
y(0)<= (i and(not s(1)) and (not s(0))); port (i:in bit;
y(1)<= (i and(not s(1)) and s(0)); s: in bit_vector(1 downto 0);
y(2)<= (i and(not s(0)) and s(1)); y: out bit_vector(3 downto 0));
y(3)<= (i and s(1) and s(0)); end component;
end dataflow;
begin
il: demux1x4 port map (a,b,c);
process
begin
a<='1';
b<="00" ; wait for 2 ns;
b<="01" ; wait for 2 ns;
b<="10" ; wait for 2 ns;
b<="11" ; wait for 2 ns;
a<='0';
b<="00" ; wait for 2 ns;
b<="01" ; wait for 2 ns;
b<="10" ; wait for 2 ns;
b<="11" ; wait for 2 ns;
end process;
end abc;

Testbench-------
Structual-----
entity testdemuxstruc is
entity demuxstruc is
end testdemuxstruc ;
port (y: out bit_vector (3 downto 0);
architecture abc of testdemuxstruc is
s: in bit_vector(1 downto 0); signal a: bit;
i: in bit); signal b: bit_vector (1 downto 0);
end demuxstruc; signal c: bit_vector(3 downto 0);
architecture structural of demuxstruc is component demuxstruc is
component andgate port (i:in bit;
port (a: in bit; s: in bit_vector(1 downto 0);
b,c: in bit; y: out bit_vector(3 downto 0));
y: out bit); end component;
end component; begin
component notgate il: demuxstruc port map (i=>a,s=>b,y=>c);
port ( a: in bit; process
y: out bit); begin
end component; a<='1';
signal out0,out1,out2,out3,ns0,ns1:bit; b<="00" ; wait for 2 ns;
begin b<="01" ; wait for 2 ns;
N0: notgate port map(a=>s(0),y=>ns0); b<="10" ; wait for 2 ns;
N1: notgate port map(a=>s(1),y=>ns1); b<="11" ; wait for 2 ns;
O0: andgate port map(a=>i,b=>ns0 , c=> ns1 , y=>out0); a<='0';
O1: andgate port map(a=>i,b=>s(0) , c=> ns1 , y=>out1); b<="00" ; wait for 2 ns;
O2: andgate port map(a=>i,b=>ns0 , c=> s(1) , y=>out2); b<="01" ; wait for 2 ns;
O3: andgate port map(a=>i,b=>s(0) , c=> s(1) , y=>out3); b<="10" ; wait for 2 ns;
end structural b<="11" ; wait for 2 ns;
end process;
end abc;
Behaviorial-------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX1x4 is
Port (D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end DEMUX1x4;
architecture Beh of DEMUX1x4 is
begin
process(D, S)
begin
Y <= "0000";
case S is
when "00" =>
Y(0) <= D;
when "01" =>
Y(1) <= D;
when "10" =>
Y(2) <= D;
when "11" =>
Y(3) <= D;
when others =>
Y <= "0000";
end case;
end process;
end Beh;
Testbench-----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX1x4_tb is
end DEMUX1x4_tb;
architecture Beh of DEMUX1x4_tb is
component DEMUX1x4
Port (D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal D : STD_LOGIC;
signal S : STD_LOGIC_VECTOR(1 downto 0);
signal Y : STD_LOGIC_VECTOR(3 downto 0);
begin
uut: DEMUX1x4 port map (
D => D,
S => S,
Y => Y);
process
begin
D <= '1';
S <= "00"; wait for 2 ns;
S <= "01"; wait for 2 ns;
S <= "10"; wait for 2 ns;
S <= "11"; wait for 2 ns;
D <= '0';
S <= "00"; wait for 2 ns;
S <= "01"; wait for 2 ns;
S <= "10"; wait for 2 ns;
S <= "11"; wait for 2 ns;
wait;
end process;
end Beh;
OUTPUT:
4x1 Mux:

1x4 Demux:

CONCLUSION: