Verilog assignment4

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A. Counters

1. Write a Verilog code for 4-bit down_counter with enable and load signals, on
assertion of load count value must be 3. Write a code for the testbench
and give appropriate inputs to test all possible combinations.

module down_counter(input clk,reset,enable,load,output reg[3:0]count);

always@(posedge clk or posedge reset)begin

if(reset)
count<=4'b1111;
else if(load)
count<=4'b0011;
else if(enable)
count<=count-1;
else
count<=count;
end

endmodule

testbench:

`include "exp1.v"

module down_counter_tb();

reg enable,clk,reset,load;
wire [3:0]count;

down_counter
dut(.clk(clk),.reset(reset),.enable(enable),.load(load),.count(count));

initial begin
forever #5 clk=~clk;
end

initial begin

reset =1;
clk=0;
load=0;
enable =0;
end

initial begin

#10 reset =0;

enable =1;
#20;
enable =0;

#10 load =1;

 #10 load=0;

enable =1;
#60;
enable=0;
#10;
$finish;
end

initial begin
$monitor("time: %0t | reset = %b | enable = %b | load = %b | count = %b",
$time,reset,enable,load,count);
end
endmodule

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2. Write a Verilog code for 4-bit up_counter with enable and load signals, on
assertion of load count value must be 9. Write a code for the testbench and
give appropriate inputs to test all possible combinations.

module up_counter(input clk,reset,enable,load,output reg[3:0]count);

always@(posedge clk or posedge reset)begin

if(reset)
count<=4'b0000;
else if(load)
count<=4'b1001;
else if(enable)
count<=count+1;
else
count<=count;
end

endmodule

testbench:

`timescale 1ns/1ps
`include "exp2.v"

module up_counter_tb();

reg enable,clk,reset,load;
wire [3:0]count;

up_counter
dut(.clk(clk),.reset(reset),.enable(enable),.load(load),.count(count));

initial begin
forever #5 clk=~clk;
end

initial begin

reset =1;
 clk=0;
load=0;
enable =0;
end

initial begin

#10 reset =0;

enable =1;
#20;
enable =0;

#10 load =1;

#10 load=0;

enable =1;
#60;
enable=0;
#10;
$finish;
end

initial begin
$monitor("time: %0t | reset = %b | enable = %b | load = %b | count = %b",
$time,reset,enable,load,count);
end
endmodule

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3.Write a Verilog code for 4 bit up-down counter with enable signal and load
signal, when the enable signal is asserted it counts from 0 to 15 in up
counting mode and counts from 15 to 0 in down counting mode, and upon
assertion of reset in up mode the count must go to 0 and in down mode the
count must go to 15. On assertion of load in up counting mode the count
must go to 9 and in down counting mode the count must go to 3. Write
associated testbench and give appropriate inputs to test different
combinations.

module up_down_counter (
input clk,
input reset,
input up_down,load,enable,
output reg [3:0] count
);

always @(posedge clk or posedge reset) begin

if (reset)begin
count <= (up_down==1) ? 4'b0000 : 4'b1111;
end

else if (load) begin

count <= (up_down == 1) ? 4'b1001 : 4'b0011;
end

else if (enable)begin
 if (up_down==1)

count <= count + 1;

else
count <= count - 1;
end
end
endmodule

testbench:

`timescale 1ns / 1ps

`include "exp3.v"

module up_down_counter_tb;

reg clk, reset,load,enable,up_down;

wire [3:0] count;

up_down_counter uut(
.clk(clk),
.reset(reset),.enable(enable),
.up_down(up_down),
.count(count),.load(load));

initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
load =0;
initial begin

reset = 1; enable = 0;up_down = 0; #20;

reset = 0; #10;
enable=1;
up_down=0;#10
load =1;
#20;
enable=1;#10;
up_down = 1; #10;
load =0; #60
enable=0;#5;
enable =1;
up_down=0;#50
load =1;
#20;

$finish;
end

initial begin
$monitor("Time = %t | reset = %b ,enable = %b | up_down = %b |, load = %b |
count = %b", $time, reset,enable, up_down,load, count);
end

endmodule
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4.Write a single Verilog code to implement 8bit, 16bit and 32 bit synchronous
up_down counter. With active low reset, clk and load as inputs. Whenever
the load is asserted, the counter should load a user defined value. Write a
testbench to verify the same.

module up_down_counter #(parameter size=8) (

input clk,
input reset,
input up_down,enable,load,
output reg [size-1:0] count
);
parameter load_value= 4'b0110;

always @(posedge clk) begin

if (~reset)begin
count <= (up_down==1) ? 4'b0000 : 2**size-1;
end

else if (load) begin

count <= load_value;
end

else if (enable)begin
if (up_down==1)

count <= count + 1;

else
count <= count - 1;
end
end
endmodule

testbench:

`timescale 1ns / 1ps

`include "exp4.v"

module up_down_counter_tb;

reg clk, reset,load,enable,up_down;

wire [16:0] count;

up_down_counter #(.LOAD_VALUE(4'b0110),.size(8))uut(
.clk(clk),
.reset(reset),.enable(enable),
.up_down(up_down),
.count(count),.load(load));

initial begin
clk = 0;
forever #5 clk = ~clk;
 end
initial
load =0;
initial begin

#5#5#5reset = 0; enable = 0;up_down = 0; #20;

reset = 1; #10;
enable=1;
up_down=0;#10
load =1;
#20;
enable=1;#10;
up_down = 1; #10;
load =0; #60
enable=0;#5;
enable =1;
up_down=0;#50
load =1;
#20;

$finish;
end

initial begin
$monitor("Time = %t | reset = %b ,enable = %b | up_down = %b |, load = %b |
count = %d", $time, reset,enable, up_down,load, count);
end

endmodule

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B. Registers

1. Write a Verilog code for a Serial in serial out shift register with
asynchronous active low reset and write the testbench to verify the same.

module siso(input clk,reset,din,output reg dout);

reg[3:0]shiftreg;
always(@posedgeclk or negedge reset)begin
if(!reset)begin
shiftreg<=4`b0000;
dout=0;
end
else begin
shiftreg<={shiftreg[2:0],din};
dout=shiftreg[3];
end
end
endmodule

testbench:

`include "exp5.v"
module siso_tb();
reg clk;
 reg reset;
reg din;
wire dout;

siso uut (.clk(clk),.reset(reset),.din(din),.dout(dout));

initial begin
clk=0;
forever #5 clk=~clk;
end

initial begin
reset = 0;
din=0;

#10 reset=1;
din=1;#10;
din=0;#10;
din=0;#10;
din=1;#50;
reset=0;

$finish;
end

initial
$monitor("time = %t |, din = %b |, clk = %b | reset = %b | dout = %b",
$time,din,clk,reset,dout);

endmodule

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2. Write a Verilog code for a Serial in parallel out shift register with
synchronous active low reset and write the testbench to verify the same

module Sipo(input clk,reset,din,output reg dout);

reg[3:0]dout;
always@(posedge clk or negedge reset)begin
if(!reset)
dout<=4'b0000;
else
dout<={shiftreg[2:0],din};

end
endmodule

testbench:

`include "exp6.v"
module sipo_tb();
reg clk;
reg reset;
reg din;
wire dout;
 Sipo dut(clk,reset,din,dout);

initial begin
clk=0;
forever #5 clk=~clk;
end

initial begin
reset = 0;
din=0;
#10 reset=1;
din=1;#10;
din=0;#10;
din=0;#10;
din=1;#50;
reset=0;

$finish;
end

initial
$monitor("time = %t |, din = %b |, clk = %b | reset = %b | dout = %b",
$time,din,clk,reset,dout);

endmodule

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3. Write a Verilog code for a Parallel in parallel out shift register with
synchronous active high reset and write the testbench to verify the same.

module pipo(input clk,reset,din,output reg[3:0]dout);

always@(posedge clk or negedge reset)begin

if(!reset)
dout<=4'b0000;
else

dout <= din;

end
endmodule

testbench:

`include "exp7.v"
module pipo_tb();
reg clk;
reg reset;
reg din;
wire dout;

pipo dut(clk,reset,din,dout);
 initial begin
clk=0;
forever #5 clk=~clk;
end

initial begin
reset = 0;
din=0;
#10 reset=1;
din=1;#10;
din=0;#10;
din=0;#10;
din=1;#50;
reset=0;

$finish;
end

initial
$monitor("time = %t |, din = %b |, clk = %b | reset = %b | dout = %b",
$time,din,clk,reset,dout);

endmodule

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4.Write a Verilog code for a Shift register with asynchronous active low reset,
with clock, reset, shift, [7:0] data_in as inputs and [7:0] data_out as output.
Whenever the “shift” is low, it should perform the left shift operation and
whenever the “shift” is high, it should perform the right shift operation. Write
the testbench to verify the same.

module shift_register(input clk,input reset_n,input shift,input [7:0]

data_in,output reg [7:0] data_out);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) data_out <= 8'b00000000;
else begin
if (shift == 0) data_out <= {data_out[6:0], data_in[0]};
else data_out <= {data_in[7], data_out[7:1]};
end
end
endmodule

testbench:

`include "exp8.v"
module tb_shift_register;
reg clk;
reg reset_n;
reg shift;
reg [7:0] data_in;
wire [7:0] data_out;
shift_register
uut(.clk(clk),.reset_n(reset_n),.shift(shift),.data_in(data_in),.data_out(data_out)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset_n = 1;
shift = 0;
data_in = 8'b00000000;
#10 reset_n = 0;
#10 reset_n = 1;
shift = 0;
data_in = 8'b00000001;
#10
#10
#10
#10
shift = 1;
data_in = 8'b10000000;
#10
#10
#10
#10
#10 $finish;
end
initial
$monitor(" time = %0t | reset = %b | clk = %b | data_in = %b | data_out = %b",
$time,reset_n,clk,data_in,data_out);

endmodule

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C. SERIES GENERATOR

1.Write a Verilog code to generate fibonacci series

module fibonacci_generator(input clk,input reset_n,output reg [7:0] fib_out);

reg [7:0] prev1;
reg [7:0] prev2;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
prev1 <= 8'd1;
prev2 <= 8'd0;
fib_out <= 8'd0;
end
else begin
fib_out <= prev1 + prev2;
prev2 <= prev1;
prev1 <= fib_out;
end
end
endmodule

testbench:
`include "fibonacci.v"
module tb_fibonacci_generator;
reg clk;
reg reset_n;
wire [7:0] fib_out;
fibonacci_generator uut(.clk(clk),.reset_n(reset_n),.fib_out(fib_out));
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset_n = 0;
#100 reset_n = 1;

#80 $finish;
end
initial begin
$monitor("Time: %0t | Reset_n: %b | Fibonacci Out: %d", $time, reset_n, fib_out);
end
endmodule

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2.

module boolean(output wire Q, input A,B);

wire C,D;

assign C =~(A|B);
assign D= ~B;
assign Q = ~(C&D);
endmodule

testbench:

`include "exp10.v"

module bool_tb();

reg A,B,C,D;
wire Q;

boolean dut(Q,A,B);

initial begin
A=0;B=0;
#10;
A=0;B=1;
#10;
A=1;B=0;
#10;
A=1;B=1;
#20;$finish;
end
initial
$monitor(" A = %b | B = %b | OUT = %b",A,B,Q);
endmodule

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