Implementation of Verilog HDL in Calculator

Design with FPGA Simulation

Shamsiah binti Suhaili Kayle Jacqueline anak Kumar Norhuzaimin Julai
Department of Electric and Electronic Department of Electric and Electronic Department of Electric and Electronic
Engineering Engineering Engineering
Faculty of Engineering Faculty of Engineering Faculty of Engineering
94300 Kota Samarahan, Sarawak 94300 Kota Samarahan, Sarawak 94300 Kota Samarahan, Sarawak
[email protected] [email protected] [email protected]

Maimun Huja Husin Mohd Faizrizwan Mohd Sabri Asrani Lit

Department of Electric and Electronic Department of Electric and Electronic Department of Electric and Electronic
Engineering Engineering Engineering
Faculty of Engineering Faculty of Engineering Faculty of Engineering
94300 Kota Samarahan, Sarawak 94300 Kota Samarahan, Sarawak 94300 Kota Samarahan, Sarawak
[email protected] [email protected] [email protected]

Abstract— A calculator is a device that can be found in daily physically smaller. FPGA designers have to create designs
life. This paper proposed the design of a calculator using Verilog that meet the essential criteria that other designers can
HDL. A series of synthesizable Verilog code was created and understand for performing the chip under worst-case
simulated on Quartus II 15.0. The design of an 8-bit calculator temperature. Besides, the process variation conditions are
can solve mathematical operations such as addition,
reliable, testable and can be proven to meet the specification
subtraction, multiplication, division, square and cube functions,
square root and factorial. This calculator consists of eight-digit and do not exceed the power consumption goals. Therefore,
numbers. In this paper, among the family devices in Altera, the designers write hardware description language (HDL)
Cyclone V was used to perform the simulation process. The code that will be used for synthesis, and the code will be
outputs are shown in the RTL viewer and waveform simulation implemented in the hardware chips. Simulation and
of the calculator design. The implementation of a calculator was operational testing of the outputs using Verilog are vital as
successfully designed using Verilog HDL in terms of digit they help avoid the error, which may cost much in silicon
numbers and the operation of the calculator function. turns and schedule delays [5 - 13]. The Verilog simulation
provides no-cost experiment, and the software tools are cheap
Keywords—Calculator, Verilog, Digital design, Mathematical
of free for testing equipment in FPGA logic [14]. Hardware
operation
Description Language such as Verilog HDL and VHDL was
I. INTRODUCTION used to create systems on chips with schematics. RTL is the
design abstraction that controls the modeling of a
The calculator is an electronic hardware or software synchronous digital circuit in the digital signals between
device that can carry out simple arithmetic operations such as hardware registers in the digital circuit design and performs
addition, subtraction, multiplication and division. A scientific logical operations on the signals. There are lots of research
calculator has some advanced operations such as have been done related to calculator design such as calculator
trigonometry function, hyperbolic function, exponential design with RISC (64 bit) architecture using Verilog and
function and logarithmic function, which could solve FPGA, Translation of Division Algorithm into Verilog HDL,
complicated mathematics problems. The invention of A New ALU Architecture Design using Reversible Logic,
calculators has reduced the required time to explain complex 12-Bit Verilog Calculator with Trigonometry Functions,
figures and common errors when digits are calculated by Simple 8-Bit Calculator Design Bit Slicing Technique and
hand [1, 2]. FPGA Prototyping, Simplified VHDL Coding of Modified
Scientific calculators support even more transistors in the Non-Restoring Square Root Calculator, A New Algorithm
integrated circuits to carry out the performance of advanced for Designing Square Root Calculators based on FPGA with
mathematical calculations. The inputs data to the calculators Pipeline Technology [15 - 21].
are processed in binary form. The integrated circuit will then
convert the decimal numbers into a binary number system, II. OBJECTIVES
which in the base-two system. Integrated circuits use the This research focuses on the design of a Verilog HDL
binary strings of data to control the transistors for the calculator based on FPGA. The improvement of this
performance of mathematical calculations. Once the calculator can be accomplished by adding the function and
mathematical operations are completed, the binary data will the calculator's digit number. The objective of this study is to
be converted back into the base-ten system. The output will design eight digits calculator with several different functions
appear on the display screen [3, 4]. Adder is formed by using Verilog HDL.
combining several logic gates to get a complex circuit.
Different combinations of logic gates in the chips can III. DATA TYPE AND FLOW OF THE DESIGN
perform various mathematical calculations like addition, Figure 1 shows the block diagram of the data type and
subtraction, multiplication and division.
flow of the calculator design. First, the input values were
The digital design developers face challenges to create
given to the design, which is in decimal form and converted
faster designs with more significant numbers of gates and

978-1-7281-9293-2/20/$31.00 © 2020 IEEE

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 into binary form for data processing purposes. The calculator
conducts several sequential operations in their binary form,
such as addition, subtraction, multiplication, division, square
& cube function, square root, and factorial feature [16 - 22].
The data were converted from the asynchronous unit to the
synchronous unit in the push-button section. The calculated
output data in binary form are then translated to BCD format
for the functioning at the seven-segment unit. The
mathematical operations' output results are produced by
lighting up the different positions of the 7-segment LEDs to
display the digit. There are nine sets of 7-segment LED
provided for output. Eight of them represented the number
digits of the calculation result. The other one on the most left
side represented the sign of the number.

Fig. 2. Block diagram of the design

In both ‘syncro’ and ‘syncro10’ modules, data in the

synchronous unit is converted from asynchronous unit
to synchronous unit. ‘syncro’ module involves 1-bit
Fig. 1. Data type and flow width of data conversion while ‘syncro10’ involves 10-
bit width of data conversion. In the ‘syncro’ and
Figure 2 shows the block diagram of the calculator. The
‘syncro10’ modules, the input data are converted from
research development is carried out using Verilog HDL on
Altera Quartus II software. The calculator design is divided the asynchronous unit to the synchronous unit. In the
into several essential parts written in several modules in the asynchronous counter, different flip flops are triggered
Verilog HDL language and activated with the waveform files with the different clock are triggered. While in the
and RTL viewers separately. The calculator top module in synchronous counter, all flip flops are triggered
this project design is named as ‘calctop’ module. The overall simultaneously with the same clock.
modules included in this top-level module are ‘calc’,
‘syncro’, ‘syncro10’, ‘binled’, ‘bintobcd’, and ‘ledout’. After the result in binary form has been computed,
the ‘bintobcd’ module translated the data set in binary
All the computational operations and functions are carried form to BCD format. For the module ‘ledout’, the data
out in this module. From the block diagram, as shown in in BCD format is translated to an LED-out format.
Figure 2, inputs from the ‘push’ section are received in the
‘binled’ module is for the code translation part, which
block ‘dectobin’, which carried out the process of converting
the input data from decimal form to binary form. The output the computed data in BCD form to the seven
computation of data is carried out in the function segments LED provided.
‘DECIMAL’. The binary input data is loaded into this A. The bit width of the register
function to register A. Register A function returns the number
It is important to evaluate the bit width range of the
used in the memory. Register B stored the input number
registers so that the design of the calculator can perform eight
memory for processing purposes on the 7-segment LED
digit calculations. The bit widths of the registers are decided
screen. The operators implemented, all clear (AC), clear entry
according to the number of digits. Since the data inputs for
(CE), add, subtract, multiply, divide, exponential, square
register A is within 0 to 99999999, which means that 0 to
root, factorial, and equal are included in the design.
101111101011110000011111111 in its binary form.
Therefore, the bit width for register A is 27 bits. In register
B, the values of 99999999 add with 99999999 got the total
number of 199999998. The range of values in decimal form
is from -199999998 (-99999999-99999999) to 1999998
(99999999+99999999). When converted the values of
199999998 to its binary form, it is
1011111010111100000111111110, and it has 28 bits.
Formula of the total number of bit width 2 is used. n
represent the number of bits. So 2 = 2 = 268435456.
Decimal of 268435456 convert to binary form
10000000000000000000000000000. Memory address must
be in binary form. The register B has 29 bits.

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 B. Overflow following state, which is ‘HALT’, where REGA<=0,
Overflow occurs when the size of the number exceeds the REGB<=0, operator<=0, and count < = 0, the overflow
maximum range of bits allowed in the registers. In this paper, occurs. This is the custom where you need to insert the ‘ac’
the inputs must be limited in the range from -99999999 to button. The ‘ac’ is responsible for clarifying the calculator
99999999, otherwise, overflow. The overflow of the design and changing functions. Once again, the program will return
is calculated based on the operation of the decimal mode. The to the ‘DECIMAL’ state.
input values must be larger than -99999999, with the signed
binary form of
0000_0101_1111_0101_1110_0000_1111_1111. When
converted to its 2’s complement, the value is
1111_1010_0000_1010_0001_1111_0000_0001. Hence, it
becomes 4194967297 when its 2’s complement binary value
is converted back into decimal form. On the other hand, the
input values must not exceed 99999999 as this is the
maximum value for an eight-digit calculator.
C. Synchronous circuit
Flip flops are made of a latch with enable input and an
edge detector circuit. The input to the edge detector is a signal
called ‘clock’. A clock signal is a square wave with a fixed
Fig. 3. FSM of a calculator
frequency. A positive edge triggered flip flop was the edge
circuit that generates pulses during rising edges.
n-bit Shift Register is connected serially. The flip flops IV. RESULT AND DISCUSSION
share the same reset and clock signals. The result is a counter Figure 4 shows the RTL viewer of top-level module
where only a single bit has a different value for two design based on the code in the appendix. The top-level
consecutive counts. All the flip flops share the asynchronous module was named with ‘calctop’. The overall modules,
signal ‘reset’, which sets the initial count. n-BIT Register is a ‘calc’, ‘syncro’, ‘syncro10’, ‘bintobcd’, ‘binled’, and ‘ledout’
collection of ‘n’ D-type flip flops, where each flip flop were included in the top-level module. There are 14 inputs
independently stores one bit. The flip flops are connected in pin and 15 outputs pin name in the design. Next, 11 syncro
parallel. They also share the same reset and clock signals. blocks and 1 syncro10 block. Syncro depends on the user
D. Binary to BCD translation which function will they be using, the data will enter the
There is 27 bits width required by register A and 29 bits ‘calc’ module. In contrast, syncro 10 depends on the number
for register B. Since the maximum value of the input in this that the user has key in. All the data will enter the ‘calc’
calculator design is 99999999, the binary result has a bit module. Afterward, calculation main module ‘calc’, where all
width of 27 bits to be translated into BCD form. The data the calculation of addition, subtraction, multiplication,
must be translated into the BCD format to be displayed on the divide, exponential power of 2 and 3, factorial and square root
seven segments LED. There are eight LEDs to display the formula was processed. This module also includes the
computed result and another one to represent the result's sign. process of the register bit width and the overflow of output.
Lastly, the ‘binled’ module which functions to transport the
E. Digit count information from the ‘calc’ module to the output which is
It is important to arrange the position of the digit count in ‘ledout’ to be displayed on seven segments LED, inside
the calculator. The function of “*10” and “+” shifts the output ‘binled’ module has a ‘bintobcd’ module and ‘ledout’
at the 7-segment LED display. Each time data input to the module.
system, the output at the display will move from the very right
side to the left side.
Figure 5 shows the waveform summary in the
Report Timing report. The circuit implemented was on
F. FSM for the calculator the Cyclone V family device. Cyclone V has the highest
Figure 3 illustrates the finite state machine of a calculator. number of total registers. The size of registers indicates
The finite state machine (FSM) summarizes the various the data that the system can be used at any given time.
circumstances of feedback from the anticipated statistics to In this circuit, the timing requirement is specified to
the operation scheme. ‘DECIMAL’ is the initial state, which 20.0ns clock. The amount of time for data to be present
is the alpha of the measure. The 10 keys assignment compute at an input pin until the clock signal clocks at the
as input from this standpoint. Just as count<=count+1, register is asserted at the clock pin, which feeds a
thereupon REGA<=REGA*10+d. When the function ‘ce’ register through its data or activates inputs. The setup
that erases the last figure or operation registered, it is inserted slack value in this circuit is 12.711ns, which is positive
at instant REGA <=0 as count <=0. When the mathematical means it meets the time requirement. The clock delay is
operations are registered, the state will shift. ‘OPE’ is the
4.985ns, represents the time between the launch at the
following state. The out func =~ b+1 at ' OPE ' is (b[28]==1),
pin of the device and the clock inputs of the
otherwise it is out func = b. Then the system moves to the

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 source/destination flip-flops. The required data showed operation, the second input values can enter Register A.
the time the data would have arrived at the flip-flop The final values enter Register B. It transmits the
destination by data delay takes by 5.758ns for a signal computed data in register B. Register B stored the input
to propagate from source to destination. The diagram number memory for processing purposes on the output.
shows that the data arrives at its destination before the Suppose the user selects the operation, such as the
time required to arrive. Therefore, the timing constraint addition. In that case, the multiplexer switches from 0
is satisfied. to 1, as it implies in a high or active state. Other
operations are subtraction, multiply, divide, square,
cube, square root, and factorial.
Based on Figure 6, two inputs from the ‘decimal’
signal loaded to register A are 96345 and 7812. The
operator selector is ‘add,’ which represented the
addition operation. The computed result is stored at
register B, 104157, and output at the ‘out’ waveform.
This means that when the number 96245 is added with
7812, the output is 104157. All the other operations
have the same method to get the final output.
96345 7812

104157

Fig. 6. Waveform simulation of the ‘add’ function.

Fig. 4. RTL view for top-level module ‘calctop’ Figure 7, 8, 9, 10, 11, 12, and 13 show the waveform
simulation results of different function of calculator design
using Verilog HDL in this paper such a subtraction,
multiplication, division square, cube, square root and
factorial respectively.

Fig. 5. Waveform summary in Report Timing

Figure 6 shows an example of the waveform

simulation involving addition. The clock was inserted
as 20ns per period. The ‘equal’ waveform was always
Fig. 7. Waveform simulation of the ‘sub’ function
put in a high position. According to the proper state, the
‘reset’ waveform was placed in a d flip-flop type to
handle the calculator design flow. Desired values are
inserted into the calculator’s design by pressing the
values in their binary form into the decimal waveform.
Desired selected operations can be selected by putting
their waveform high.
The binary input data is loaded into this function to
register A. Register A function returns the number of Fig. 8. Waveform simulation of the ‘mul’ function

users in the memory. Register A takes the first input

number. After that, the second input number begins
again from 0. Once the user chooses the desired

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 designing complex digital circuits using Verilog HDL. The
calculator designs can only generate an integer answer and
produce 8-digit output, which means that if the answer
includes decimal numbers, the result lack precision. It is
suggested for future work to get a more precise result;
floating-point includes getting an accurate output. Lastly, it
is recommended to include more mathematical operations to
solve complex mathematical problems, such as logarithmic,
Fig. 9. Waveform simulation of the ‘div’ function exponential, and trigonometric functions.
ACKNOWLEDGMENT
The author would like to thank Universiti Malaysia
Sarawak (UNIMAS) for providing opportunity and facilities
to support this project.

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Fig. 10. Waveform simulation of the ‘sq’ function
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