ASSIGNMENT

Oraw the crcuit diaqaam of an NMOS inver ter and explain its
operation Derive the expsession for Pull- up to Pull - Doon RaHo for
an NMOS Inverter deúven bu another NM0S
Inverter
An inver ter circuit is a very im portant
circut for produ Cih g
a complete ange of dogic circuis This needed for Aestorih
Logic leveLs , for NAND and NOR gates anct for scquenhal and memo'y
ciTCuis of vari ous forms A simple invetter cirCUit con be conshructed
USing a transitor SOuTCe
connected to qaound and a load
SesistoY of conne cte d from the dsan o
the posifive spply erail VpD
The output s taken from the drain and +he inpu t applied
betuoeen qate and qoounc But, durinq the fabrica hion resistovs
are not Convenien tly pcduCe d on the ilico n subetra te and even
Smal valuce of stesis tor s occuP excccssively larqe areas Hence
Some Orhes form f doad aesistance s 0sec A more Convenient
to solve thés paoblem is to Use a deplehion node
+ransístor as the doad, as

Vout

GND
teY are
featUres. of the n-mos inver
The Salient
tor the gate s connecte d to
For deplehon mode tranSis
the
the sourCe s0 it alu ays on +he
devi Ce s callecdoon
the depletion mode
" in thu ConFiquration cement
mode device the pull
Full p (PO) and the enhan
CP D) +ransistor
output the corrent ds
wih no cuTrent draton from
the
be equal
for both +Tansistorg must
 vas Cenh) 08 Vop

Vqs(enh)
vqs(dep) o- 5Voo
vqs(enh) 04vDD
vgs(enh)r o2vpD
O5VDp vgscenh)
ks (dep)
Ihe ransfer chora Cterictc is dron by daking Vàs 0n x-axis
and Ids on y- axis for both
enhancement and depletiarn mode
+ranoistos6 Go to obtain the inver ter rans fer char Ccteristic fox
Vqs 0 depletion mode character istic cuTVe & super imposed on
th6 foamily of Cerves for Hne enhancemen t mode device and
from the goraph it can be een that m aximu m voltag e acrOSS
the depleton mode transistor frcm the qeaph it is clear that as
Vin C: Vqs pd +ransistor) excccds the culldoon threshold voltage
cUTYent beqins to floo The outtpu t voEaqe Voot thus cecreases
and the &ubcqueent iMCTeases Vin uill Cause the pull down
tYansic toY to Come out of eettti eaturation and beco me sesishive
Vout Vout Vin.

Decreasnq
zpo (zpd

increosre
2 pu zpd
ViD
Vin 0 5VDD VDD
similay
An inverter is diven fom the outpol of Cunother
inyerter Consider the depletion mode transis toY for ohich Va s-o
under cul condi Hons, and also assume that in order to
Cas COde inveyteTB with 0Ut deqoadation the Con di ton

inverter threshol d, e set

aYound the aTe in Satoration
T eqeal marqins point borh tansctos
At ths
Viny - O5Vpp
axite that
and we can
 bCatuTakon
equahOh
The ceplction mode
> Ids rk

(-VEd) ince Vqso

LPU
The eahancernent mode
Ids = k Wpd Cviny - V)
Lpd Since Vgs= Vin V
equahna csince currents ame the ome) Que
have
wipd
LPd
criny - Ve) - wWpu Cd)
LPU

wibere wp-d, Lpd, pU and LPU are the

the ful - down and full qp widths and Leng the of
Zpd Lpd transistor8 respect vel
wpd WPU
Cvinv- VE)²
zpd
Vin VE- VEd
Jzpo (Zpd
Substi fute

rinv -05Y pp Cfor equal magin)

Jzpolzpd

o3= 06
JzpolzPd

on both sides
squaing

inverter and explan

O paaw the circoit diaqam of a CMOS
opesaton Draw the transfer
about the Ave drsin t egions of
characteristtC with p ra Hos
 VeD

oVot

ia cMOS VsS
operation: nverter clrcuit
Peqion A when vin oC Loqic
*P transletor fuly o)
turned
* N
oNCSatUraion
Tanslstor fully turned OFF
no CCutoff)
acqjon)

is
Current flowS throUqh the invertcr and the ODtpot
dise ctlyconnectcd to voD throuqh the trans's for A good
toqic i oUtput voLtaqe s thu%
Reqion e: when Vin Voo CLogic )poesent at oUtput
*P tanslstoY fUtinq
N transistor
turncd ofF CCotofP)
NO Curren t
fully
toaned on Csaturation)
fHows through the nverter and a goo d toqic o
appeaTS at tthe output
Reqion 6: The input vOLtaqe has imcre ased to level nlhich
jugt excced 3 the thveshol d voLtage Of the NMOS translsto
The NMOG Eranststor conducts and has a darge voltage
betuo en SOUTCe and dsccuh. So it s Satu vation. The p. transict
aso conduching but onty mal voltaqe across ,it and
opescates in esistive aeqion
Reqion D simi (ar to eqionB bot with ooles o e and N
+ranstEtors AeverSed
Region c: tE ig the steqion in hich the inverter exhibi s gain
nd in both cutoff and sa tora tion.
Cegions
Yator& 121:la |5|
Usent
Cbeucen

Vin
 VDD

Be

VSS
7Vin

fqure (o): Trend vDD|

n
4
Kihat are Lanbda bas ec design trangfer
chara Cteylstic with p raio

nMos, pMOS and CMDS ranckstor rules Cplatn in the detall about
Lombdo based clesiqn ues desiqn aoles with dÉaqsama
Dea gn Jtutes can be scaled
intens of '2 wih'ch s the siHe of
4he Smattest element in
the
t nhen devtces shink. dauoutstaycut
nexd not be completety sedesqne o
All features Can be mecusu ved m
k54 Choosing a value for A, aL intcqal mutkple ot
dimenions stt ata scabale
tayout
Scalable Layout are advaniages a Chip be come faster as
Slge simllar
Minimum idtb of polysltt Con and cüffosion Lint s '22
Minimum taidh DE meraL I '32 ond metal s s HA
Cepesaion betoeen pdysilicon to polysiticon is 22
" Separatton be toeen meralLt s'8A ond metal 25 'HN.
" misnum speration blw diffoslon 3A
" metal unes Can pass over botn diffacion and polsi lico n kit heut
electrical etfect
"Aspce betubcen potysilicon and mctal condition
betDeen enhancennent and
Sepasation of tA ghoutcl be
deplehon
 n-diffus ian
P-diffusion mintrnu
oidtb

3)

polysiucon
|
MekalU
2

hmos enharncemode
+ransis tor hmos depletpe mode
transs tor
 pmas enhance ment
mode +ransistor
2 minimon

Traneistor Desiqn rules

Daw the cIrcuit
diaqeam
©peTaton DerVe +he expressior for
NIMOS mverter and expla'n is
pol(- oP to polldown raHo o
NMOS inverfe r drven +hrocgh one or morc paes translsto o3
* tn fiqure uhich the
input to inerter 2 COmnes from the
OLetput Of inerter I but pass es through one or ore hMos
tTanSisOrS Used s Sitches in Series
are concer ed that coonection ef pass ransis tor8 SeDieS
deqada the toqic i Aevel into inverter
Dtha t the output coil not be a proper uoqic o tevel-hrd 3
thaty
+ The csitical CondeHon t8 when point A s at o voltS a n
at voD, bu the vo(Eage imto inverter 2 at point c
now AEduced from vpp by the thresho ld voltage of the
Bevtes pass tranefstor with all, pass tansstor gates connectca
to vpo there 8 a toss of Yip hoLo ever many are connected in
series Stnce ro curent flocOs through them and they can be
no vo(tage d%o tbe termi nals- There fo re the inpu volta qe to
iMverer i8
hverter VDD

tnverter 2

vpD-Vp Vout

pulldocon atio's fo imvexting loq'c coupled by pUs

Peul op to
trcngj stor
Vin) Vo- V p
where transistor
Ytp +hreshold vol tage for a pass
oe get
mUst na ensore +hat fos ttus npot voltaqe
c@se for nverter )
the same votaqe as cUOuld be the

driven with inpot - Vpp

 Vpp

Depletion
Delpletin mode
mole

Erbance mont
rmode
eohancemert
moce

GND
Invertcra coith p VpO-Vp
Iverter IIp=VDD
* Consider tnverter uith npot VppIf the input i8 at vop, then
+he P d ranssto T2 s Coodring bo b orth a docu volkaqe
ackOSS itj thec fore, it i8 m is secltive steq ion oepxesenec d
bq Ri im fiqore
CUrDeot OYCe
FoY the Pd tTanslstor
Tds k. klpd [Cvep-ve) Vasi- Vag
Lpd

P= Vds) Lpdi
Ids YDD-V - VdSi

lpu (-Vtd)

The poco duct

(-VE
Zpor

Pz=zp'CVo - vtp) -V4

-Vtd)

tence
Zpdz
 There foe.
Zpuz 2 Zpul CVpp- Vt)
2p da Zp d Cvpp- Vep- VE)

Zpd Zp d os
Thercto re
3 mpewevtt -tetno-inprt NAND 0iCc functon cisi
CMOS ogic style. AEO ctan tts stik daoam shoniy

pMOS

Vout
Vin
NM0S

VeS

velloN

Layouta
 ahot Tvanasto eted desqnoles Coi
te ExplcùM
2Hm CMOS) mivnivvn si7eS nd ovops With
setevctt diaquciwe.
2Hm
24w mniwcmM ejan
Miuin

RRIn Pte 3m
miu. 5 m

estensTo
ntYpe enhanemet P-tYpe enhaCemen+

25Hm

neyad qaté
tin-eesion POlY2 ain- etesion
2Hw -Polya

n-tYpo ennoCMet
p-type enoeWet