Experiment 4

Implementation of Combinational Logic Circuits in Structural modelling using

Aim: To Write a program for following Logic circuits in Structural modeling using VHDL and verify the
results.

(i)Half adder, (ii) Full adder (iii) Four bit RCA (iv) Parity Generator and (iv)
2X4 decoder

Software Used: XYLINX

Theory

Structural Modeling in VHDL

The architecture body of structural modelling consists of three parts

Component declaration, signal declaration and Component Instantiation

In Component declaration the name and interface of the component is declared

component component_name is

[port (list-of-interface-ports);]

end component;

The component name may or may not refer to the name of an entity already existing in a library. If it
does not, it must be explicitly bound to entity. The list-of-interface-ports specifies the name , mode and
type of each port of the component in a manner similar to that specified in an entity declaration.

A component instantiation statement defines a subcomponent of the entity in which it appears. It

component-label: component-name port map ( association-list) ;

The component-label can be any legal identifier and can be considered as the name of the instance.

The component-name must be the name of a component declared earlier using a component
declaration.

The association-list associates signals in the entity, called actuals, with the ports of a component, called
locals
There are two ways to perform the association of locals with actuals:

1. positional association, 2. named association.

In positional association, an association-list is of the form actual1, actual2, actual3, . . ., actualn

Each actual in the component instantiation is mapped by position with each port in the component
declaration.

That is, the first port in the component declaration corresponds to the first actual in the component
instantiation, the second with the second, and so on. Consider an instance of a NAND2 component

. -- Component declaration:

component NAND2

port (A, B: in BIT; Z: out BIT);

end component;

-- Component instantiation:

N1: NAND2 port map (S1, S2, S3);

In named association, an association-list is of the form

local1 => actual1, local2 => actual2, ..., localn => actualn

component NAND2

port (A, B: in BIT; Z: out BIT);

end component;

-- Component instantiation:

N1: NAND2 port map (A=>S1, B=>S2, Z=>S3);

structural modelling for half adder

HALF ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity HALFADD is
 Port ( X : in STD_LOGIC;

Y : in STD_LOGIC;

S : out STD_LOGIC;

C : out STD_LOGIC);

end HALFADD;

architecture Behavioral of HALFADD is

component xor_gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

XOR_OUT : out STD_LOGIC);

end component;

component and_gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

AND_OUT : out STD_LOGIC);

end component;

begin

X1: xor_gate port map(X,Y,S);

A1: and_gate port map(X,Y,C);

end Behavioral;

FULL ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity FULLADD is

Port ( X_in : in STD_LOGIC;

Y_in: in STD_LOGIC;

Z_in: in STD_LOGIC;

S_out: out STD_LOGIC;

C_out : out STD_LOGIC);

end FULLADD;

architecture Behavioral of FULLADD is

component HALFADD is

Port ( X : in STD_LOGIC;

Y : in STD_LOGIC;

S : out STD_LOGIC;

C : out STD_LOGIC);

end component;

component or_gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

OR_OUT : out STD_LOGIC);

end component;

signal s1,c1, c2:STD_LOGIC;

begin

H1: HA1 port map (X_in,Y_in,s1,c1);

H2: HA1 port map(s1,Z_in,S_out,c2);

O1: or_gate port map (c1,c2, C_out);

end Behavioral;
FOUR BIT RCA

Library IEEE;

Use IEEE.STD_LOGIC_1164.all;

entity fourbitRCA is

port ( x1: in STD_LOGIC_VECTOR (3 downto 0);

y1: in STD_LOGIC_VECTOR (3 downto 0);

cy : out STD_LOGIC; z1:out STD_LOGIC_VECTOR(3 downto 0));

end fourbitRCA;

--Component declaration

architecture RCA_ST of fourbitRCA is

component FULLADD is

Port ( X_in : in STD_LOGIC;

Y_in: in STD_LOGIC;

Z_in: in STD_LOGIC;

S_out: out STD_LOGIC;

C_out : out STD_LOGIC);

end component;

-- signal declaration

signal cy0,cy1,cy2: STD_LOGIC;

-- component Instantiation

FA0: FA port map(x1(0),y1(0),’0’,z1(0),cy0);

FA1: FA port map(x1(1),y1(1),cy0,z1(1),cy1);

FA2: FA port map(x1(2),y1(2),cy1,z1(2),cy2);

FA3: FA port map(x1(3),y1(3),cy2,z1(3),cy);

end RCA_ST;
9 bit Parity Generator

It is combinational circuit that accepts an n-1 bit stream data and generates the additional bit that is
to be transmitted with the bit stream. This additional or extra bit is termed as a parity bit. In even
parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and the parity
bit is ‘1’ if there are odd number of 1s in the data stream. In odd parity bit scheme, the parity bit is ‘1’
if there are even number of 1s in the data stream and the parity bit is ‘0’ if there are odd number of 1s
in the data stream. Let us discuss both even and odd parity generators.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity nine_bit_parity is

Port ( D : in STD_LOGIC_VECTOR (8 downto 0);

even_out : out STD_LOGIC;

odd_out : inout STD_LOGIC);

end nine_bit_parity;
architecture Behavioral of nine_bit_parity is

component xor_gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

XOR_OUT : out STD_LOGIC);

end component;

component not_gate is

Port ( A : in STD_LOGIC;

NOT_OUT : out STD_LOGIC);

end component;

signal E0, E1, E2, E3, F0, F1, H0: STD_LOGIC;

begin

XE0: xor_gate port map (D(0), D(1), E0);

XE1: xor_gate port map (D(2), D(3), E1);

XE2: xor_gate port map (D(4), D(5), E2);

XE3: xor_gate port map (D(6), D(7), E3);

XF0: xor_gate port map (E0, E1, F0);

XF1: xor_gate port map (E2, E3, F1);

XH0: xor_gate port map (F0, F1, H0);

XODD: xor_gate port map (H0, D(8), odd_out);

XEVEN: not_gate port map (odd_out, even_out);

end Behavioral;
2X4 Decoder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity two_four_dec is

Port ( EN : in STD_LOGIC;

S : in STD_LOGIC_VECTOR (1 downto 0);

Y : out STD_LOGIC_VECTOR (3 downto 0));

end two_four_dec;

architecture Behavioral of two_four_dec is

component and3in is

Port ( l : in STD_LOGIC;

m : in STD_LOGIC;

n : in STD_LOGIC;

p : out STD_LOGIC);

end component;

component not_gate is
 Port ( A : in STD_LOGIC;

NOT_OUT : out STD_LOGIC);

end component;

signal S0bar, S1bar:STD_LOGIC;

begin

I1: not_gate port map (S(0), S0bar);

I2: not_gate port map (S(1), S1bar);

A1: and3in port map(EN,S0bar, S1bar, Y(0));

A2: and3in port map(EN, S(0), S1bar, Y(1));

A3: and3in port map(EN,S0bar, S(1), Y(2));

A4: and3in port map(EN,S(0), S(1), Y(3));

end Behavioral;