ADC DNL

• DNL=-1 implies missing code

• For an ADC DNL < -1 not possible Æ undefined
• Can show:
al l i
∑ DN L[i ] = 0

• For a DAC DNL < -1 possible

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 23

DAC Differential Nonlinearity

• To find DNL for DAC

– Draw end-point line from 1st point to last
– Find ideal LSB size for the end-point corrected
curve
– Find segment sizes:
segment [m]=V[m]-V[m-1]

s e g m e n t[ m ] − V [ L S B ]
D N L[ m ] =
V [ LSB ]

• Unlike ADC DNL, for a DAC DNL can be <-1LSB

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 24
 DAC Differential Nonlinearity

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 25

Impact of DNL on Performance

• Same as a somewhat larger
quantization error, consequently
degrades SQNR

• How much – later in the course...

• The term "DNL noise", usually means

"additional quantization noise due to
DNL"
EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 26
 ADC Integral Nonlinearity
ADC Transfer Function
INL = deviation of code transition Output
from its ideal location
INLMax
INL is also a vector INL[k] Real
If one INL # reported Ideal
ÆWorst case INL

Most commonÆ End-point:

Straight line through the endpoints is Input
usually used as reference,
i.e. offset and full scale errors are
INL
eliminated in INL calculation
INLMax
Ideal converter steps found for the endpoint
Digital
line, then INL is measured INL Curve Output

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 27

ADC Integral Nonlinearity

Best-Fit
Output
INL = deviation of code transition
from its ideal location
Real Ideal
Best-Fit
A best-fit line (in the least-
mean squared sense) fitted

Ideal converter steps found Input

then INL measured ADC Transfer Function

INL

Note: Typically INL #s smaller for

best-fit compared to end-point INL Curve

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 28
 ADC Integral Nonlinearity
End-Point
INL = deviation of code 7
transition from its ideal location
6

Digital Output Code

• Typically, end-point INL 5
reported in publications -1 LSB INL
4

-1 0 1 2 3 4 5 6 7 8
ADC Input Voltage [Δ]

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 29

ADC Integral Nonlinearity

Best Fit versus End-Point

7 +1/2 LSB INL

• Best-Fit
6
Digital Output Code

– A best-fit line (in the

least-mean squared 5
sense) -1/2 LSB INL
4 Best Fit
– Ideal converter steps is
found then INL is 3
measured
2

1 End-point INLmax =1LSB

Best-fit INLmax =+-1/2LSB
0

-1 0 1 2 3 4 5 6 7 8
ADC Input Voltage [Δ]

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 30
 ADC Integral Nonlinearity
Can derive INL by:
1-
• Construct uniform staircase between 1st and last transition
• INL for each code:

T [ m] − T [i deal ]
IN L[ m] =
W [i deal ]

2-
m −1
• Can show IN L[ m] = ∑
i =1
DN L[i ]

Æ INL is found by computing the cumulative sum of DNL

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 31

ADC Differential & Integral Nonlinearity

Example

m −1 Code # DNL INL [LSB]

IN L[ m] = ∑
i =1
DN L[i ] [LSB]
0 - -
1 0.18 0
Notice:
2 -0.55 0.18
3 0.55 -0.37
INL[0] Æ undefined
4 -0.55 0.18
INL[1]=0 5 -0.27 -0.37

INL[2N-1]=0 6 0.64 -0.64

7 - 0

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 32
 ADC Differential & Integral Nonlinearity
Example
Max.
1 DNL Code DNL INL
0.5 # [LSB] [LSB]
DNL [LSB]

0 - -
0

-0.5
1 0.18 0

-1 2 -0.55 0.18
0 1 2 3 4 5 6 7
1 3 0.55 -0.37
0.5 4 -0.55 0.18
INL [LSB]

0 5 -0.27 -0.37
-0.5 Max. 6 0.64 -0.64
-1 INL
0 1 2 3 4 5 6 7 7 - 0
Code #

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 33

DAC Integral Nonlinearity

Can derive INL by:
• Connect end points
• Find ideal output values
• INL for each code:

V [ m] − V [i dea l ]
INL[ m] =
V [ LSB]

2-
m −1
• Can show IN L[ m] = ∑
i =1
DN L[i ]

Æ INL is found by computing the cumulative sum of DNL

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 34
 DAC Integral Nonlinearity

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 35

DAC DNL and INL

* Ref: “Understanding Data Converters,” Texas Instruments Application Report

SLAA013, Mixed-Signal Products, 1995.

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 36
 Example: INL & DNL

Large INL & Small DNL Large DNL & Small INL

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 37

Monotonicity
• Monotonicity guaranteed if
| INL | ≤ 0.5 LSB
The best fit straight line is taken as the reference for determining the INL.
• This implies
| DNL | ≤ 1 LSB

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 38
 Non-Monotonic DAC
Analog
s eg ment[ m] − V [ L SB ] Output [LSB]
DN L[ m] =
V [ LSB]
7
s eg ment[ 4 ] − V [ L SB ]
6
DN L[ 4 ] =
V [ LSB]
− 0. 5 − 1 5
= = − 1 . 5[ L S B ]
1 4
2. 5 − 1
DN L[ 5] == = 1.5[ L SB ] 2.5
1 3
-0.5
2
• DNL< -1LSB for a DAC
Æ Non-monotonicity 1
Digital
0 Input
• When can non-monotonicity
cause major problems? 000 001 010 011 100 101 110 111

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 39

Non-Monotonic ADC

• Code 011 Digital Output

associated with two 111

transition levels ! 110

101
• For non-monotonic 100
ADC
011
ÆDNL not
010
defined @ non-
monotonic 001
Analog
steps 000 input
0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 40
 How to measure DNL/INL?
• DAC:
– Simply apply digital codes and use a good voltmeter to
measure corresponding analog output

• ADC
– Not as simple as DACÆ need to find "decision levels", i.e.
input voltages at all code boundaries
• One way: Adjust voltage source to find exact code trip
points "code boundary servo"
• More versatile: Histogram testing
ÆApply a signal with known amplitude distribution and
analyze digital code distribution at ADC output

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 41

Code Boundary Servo

Input
Digital i1
Code C1
A VREF fS
A<B
ADC
Digital R2 Input ADC
Comp. Under
A≥B Test
B
C2
i2

ADC
Output

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 42
 Code Boundary Servo
• i1 and i2 are small, and 111

ADC Digital Output

C1 is large, so the
ADC analog input 110
moves a small fraction
101
of an LSB each
sampling period
100

011
• For a code input of
101, the ADC analog 010
input settles to the
code boundary shown 001

000
Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
ADC Analog Input

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 43

Code Boundary Servo

Input Good DVM
Digital i1
Code C1
A VREF fS
A<B
Digital R2
Comp. ADC
A≥B
B
C2
i2

ADC
Output

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 44
 Code Boundary Servo
• A very good digital voltmeter (DVM)
measures the analog input voltage
corresponding to the desired code boundary
• DVMs have some interesting properties
– They can have very high resolutions (8½ decimal
digit meters are inexpensive)
– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line
cycles to filter out pickup in the measurement loop

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 45

Code Boundary Servo

• ADCs of all kinds are Good DVM
notorious for kicking
back high-frequency, VREF fS
signal-dependent
glitches to their analog R2
inputs ADC

C2
• A magnified view of an
analog input glitch
follows …

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 46
 Code Boundary Servo
• Just before the input is
sampled and

analog input
conversion starts, the
analog input is pretty
quiet

• As the converter begins

to quantize the signal, it start of conversion
kicks back charge
0 1/fS
time

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 47

Code Boundary Servo

DVM measures the average
• The difference between input including the glitch
what the ADC
analog input

measures and what the

DVM measures is not
ADC INL, it’s error in
the INL measurement

• How do we control this ADC converts this voltage

error?
0 1/fS
time

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 48
 Code Boundary Servo
• A large C2 fixes this Good DVM

• At the expense of longer VREF fS

measurement time
R2
ADC

C2

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 49

Histogram Testing
• Code boundary measurements are slow
– Long testing time
– May miss dynamic errors

• Histogram testing
– Quantize input with known pdf (e.g. ramp or
sinusoid)
– Measure output pdf
– Derive INL and DNL from deviation of measured
pdf from expected result

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 50
 Histogram Test Setup
VREF fS

Ramp VREF
ADC PC
Time
0

• Slow (wrt conversion time) linear ramp applied to ADC

• DNL derived directly from total number of occurrences of each
code @ the output of the ADC

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 51

A/D Histogram Test Using Ramp Signal

Digital Output
Example:
ADC
Ramp slope: 10μV/μsec Input/Output
1LSB =10mV
Each ADC code Æ1msec

fs =100kHz Æ Ts=10μsec
Analog
Æ n =100 samples/code input

n/fs
Ramp
Time

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 52
 A/D Histogram Test Using Ramp Signal
Example:
ADC

Digital Output
Ramp slope: 10μV/usec Input/Output
1LSB =10mV
Each ADC codeÆ1msec
Analog
fs =100kHz Æ Ts=10μsec
input

Æ n =100 samples/code
n/fs Ramp
Per code Time
Samples
# of

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 53

Measuring DNL
• Ramp speed is adjusted to provide large number of
output/code - e.g. an average of 100 outputs of each
ADC code (for 1/100 LSB resolution)

• Ramp test can be quite slow for high resolution ADCs

• Example:
16bit ADC & 100conversions/code @100kHz
sampling rate
(216or 65,536 codes)(100 conversions/code)
= 65.6 sec
100,000 conversions/sec

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 54
 Ramp Histogram
Example: Ideal 3-Bit ADC

200
ADC characteristics
ideal converter
7 180

6 160

Code Count
Digital Output Code

140
5
120
4
100
3
80
2 60
1 40

0 20

0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7
ADC Input Voltage [Δ]
ADC output code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 55

Ramp Histogram
Example: 3-Bit ADC with Error

ADC characteristics
200
ideal converter
7 180

6 160
-0.4 LSB DNL
Digital Output Code

140
5
Code Count

120
4
100
3
+0.4 LSB INL 80
2
60
1 40
+0.4 LSB DNL
0 20

0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7
ADC Input Voltage [Δ] ADC output code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 56
 Example: 3 Bit ADC
DNL Extracted from Histogram
140

Code Count, End bins removed

120
1- “Over-range bins”
removed (0 and full-scale) 100

80
2- Compute average count/bin
(600/6=100 in this case) 60

40

20

0
0 1 2 3 4 5 6 7
ADC output code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 57

Example: 3 Bit ADC

DNL Extracted from Histogram
1.4

1.2
Normalize:
Normalized Code Count

3- Divide by average count/bin 1

(ideal bins have exactly the
0.8
average count, which, after
normalization, is 1) 0.6

0.4

0.2

0
0 1 2 3 4 5 6 7
ADC output code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 58
 Example: 3 Bit ADC
DNL Extracted from Histogram
0.4
4- Subtract 1 from the
normalized code count

DNL = Counts / Mean(Counts)

0.3

0.2
5- Result is DNL (+-0.4Lsb in
this case) 0.1

-0.1

-0.2

-0.3

-0.4 0 1 2 3 4 5 6 7
ADC output code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 59

Example: 3-Bit ADC

Static Characteristics Extracted from Histogram
• Width of all codes derived
from measured DNL
(Code=DNL + 1LSB) 7
Reconstructed Characteristic

• DNL histogram Æ used to 5

reconstruct the exact 4

converter characteristic
(having measured only the 3

histogram) 2

• INL- (deviation from a 0

straight line through the end -1 0 1 2 3 4 5 6 7 8

points)- is found
ADC Input Voltage

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 60
 Example: 3 Bit ADC
DNL & INL Extracted from Histogram
DNL and INL of 3 Bit converter (from histogram testing)

ADC characteristics 1
ideal converter

DNL [LSB]
7
0.5
6
0
-0.4 LSB DNL
Digital Output Code

5 -0.5

4 -1 1 2 3 4 5 6
bin #
3
1
+0.4 LSB INL

INL [LSB]
2 0.5

1 0
+0.4 LSB DNL
0 -0.5

-1 0 1 2 3 4 5 6 7 8 -1
1 2 3 4 5 6
ADC Input Voltage [Δ]
bin #

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 61

ADC Histogram Testing

Sinusoidal Inputs
• Highly linear ramp signals not ADC Output- Raw Histogram
readily available (>8 to10bits) 250

• Solution: 200

ÆUse sinusoidal test signal

(may need to filter out 150

harmonics)
100

• Problem: ideal histogram is

not flat but has “bath-tub 50

shape”
0
0 500 1000 1500 2000 2500 3000 3500 4000

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 62
 A/D Histogram Test Using Sinusoidal Signals

Digital Output
At sinusoid midpoint crossings: ADC
dv/dt Æ max. Input/Output
Æ least # of samples
Analog
At sinusoid amplitude peaks: input
dv/dt Æ min.
Æ highest # of samples

Per code Time

Sinusoid
Samples
# of

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 63

Resulting DNL and INL

DNL = +1.3 / -1 LSB, missing code if (DNL<-0.9)
DNL [LSB]

-1
0 500 1000 1500 2000 2500 3000 3500 4000
code
2 INL = +1.7 / -0.69 LSB
INL [LSB]

-1
0 500 1000 1500 2000 2500 3000 3500 4000
code

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 64
 Correction for Sinusoidal PDF
• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,
“Dynamic Testing and Diagnostics of A/D Converters,” IEEE
Transactions on Circuits and Systems, vol. CAS-33, no. 8,
Aug. 1986.
– [2] IEEE Standard 1057
• Is it necessary to know the exact amplitude and offset
of sinusoidal input? No!

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 65

DNL/INL Code
% transition levels
function [dnl,inl] = dnl_inl_sin(y); T = -cos(pi*ch/sum(h));
%DNL_INL_SIN
% dnl and inl ADC output % linearized histogram
% input y contains the ADC output hlin = T(2:end) - T(1:end-1);
% vector obtained from quantizing a
% sinusoid % truncate at least first and last
% bin, more if input did not clip ADC
% Boris Murmann, Aug 2002 trunc=2;
% Bernhard Boser, Sept 2002
hlin_trunc = hlin(1+trunc:end-trunc);

% histogram boundaries
% calculate lsb size and dnl
minbin=min(y);
maxbin=max(y); lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
% histogram misscodes = length(find(dnl<-0.9));
h = hist(y, minbin:maxbin);
% calculate inl
% cumulative histogram inl= cumsum(dnl);
ch = cumsum(h);

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 66
 DNL/INL Code Test
DNL = +0.7 / -0.7 LSB, 0 missing codes (DNL<-0.9)
1

DNL [LSB]
% converter model
0.5
B = 6; % bits
range = 2^(B-1) - 1; 0
% thresholds (ideal converter) -0.5
th = -range:range; % ideal thresholds
-1
th(20) = th(20)+0.7; % error -30 -20 -10 0 10 20 30
INL = +0.7 / -0.0 LSB
fs = 1e6; 0.8

INL [LSB]
fx = 494e3 + pi; % try fs/10! 0.6
C = round(100 * 2^B / (fs / fx)); 0.4
0.2
t = 0:1/fs:C/fx;
0
x = (range+1) * sin(2*pi*fx.*t);
-0.2-30 -20 -10 0 10 20 30
y = adc(x, th) - 2^(B-1);
code

hist(y, min(y):max(y));

dnl_inl_sin(y);

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 67

Histogram Testing Limitations

• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.
• Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … Æ look at ADC output to
detect
• Noise not detected or could improves DNL
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …

Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution
ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 68
 Example: Hiding Problems in the Noise

• INL Æ 5
missing codes

• DNL "smeared
out" by noise!

• Always look at
both DNL/INL

• INL usually [Source: David Robertson, Analog Devices]

does not lie...

EECS 247 Lecture 12: Data Converter Performance Metrics © 2007 H. K. Page 69