Course Course Course L T P C

21ECC303T VLSI DESIGN AND TECHNOLOGY C PROFESSIONAL CORE

Code Name Category 3 0 0 3

Pre-requisite Co- requisite Progressive

21ECC203T Nil Nil
Courses Courses Courses
Course Offering Department ECE Data Book / Codes / Standards Nil

Course Learning Rationale (CLR): The purpose of learning this course is to: Program Outcomes (PO) Program
Specific
CLR-1: implement a given logic function using appropriate logic styles for improved performance 1 2 3 4 5 6 7 8 9 10 11 12 Outcomes
understand the MOSFET operation and processes in IC fabrication, steps in the fabrication of MOS ICs,
CLR-2:

Environment & Sustainability

and as well the layout design rules

The engineer and society

Conduct investigations of

Individual & Team Work

Engineering Knowledge
CLR-3: understand Concepts of thermal oxidation and Si/SiO2 interface

Design/development of

Project Mgt. & Finance

concepts of ion implantation, role of the crystals structures, high-energy implants, ultralow energy

Modern Tool Usage

Life Long Learning

complex problems
CLR-4:

Problem Analysis
implants and ion beam heating methods

Communication
use Verilog HDL as a design-entry language for FPGA in electronic design automation of digital circuits,
CLR-5:
Design, construct and simulate VLSI adders and multipliers

solutions

PSO-1

PSO-2

PSO-3
Ethics
Course Outcomes (CO): At the end of this course, learners will be able to:
examine the characteristics of MOS transistors and Analyze CMOS inverter and other complex logic
CO-1: - 2 3 - - - - - - - - - 2 - -
gates designed using different logic styles
design and implement digital circuits using Verilog HDL, general VLSI system components, adder cells
CO-2: - 3 - - - - - - - - - - - - -
and multipliers to address the design of data path subsystem
explain how the transistors are built, and understand the physical implementation of circuits and
CO-3: - 2 3 - - - - - - - - - - 2 -
understand physics of the Crystal growth, wafer fabrication and basic properties of silicon wafers
to learn the various lithography techniques and concepts of wafer exposure system, concepts of thermal
CO-4: oxidation and Si/SiO2 interface. Dopant solid solubility, diffusion macroscopic point, different solutions to - 3 1 - - - - - - - - - 2 - -
diffusion equation
to learn concepts of ion implantation, role of the crystals structures, high-energy implants, ultralow energy
CO-5: - 2 2 - - - - - - - - - 2 - -
implants and ion beam heating methods

Unit-1 - Introduction to Verilog HDL & Coding 9 Hour

Introduction to HDL & Verilog HDL - Introduction to Verilog HDL, modules and ports -Lexical Conventions: White Space and Comments, Operators - Numbers, Strings, Identifiers, System Names, and Keywords -
Verilog Data Types: Nets, Register Variables, Constants Referencing Arrays of Nets or Regs -Arithmetic Operators, Bitwise Operators, Reduction Operators, Logical Operators, Relational Operators, Shift Operators,
Conditional Operator, Concatenation Operator, Expressions and Operands, Operator Precedence -Verilog modeling: Gate-level modeling - Realization of Combinational and sequential circuits -Compilation and
simulation of Verilog code -Test bench -Dataflow modeling -Realization of Combinational and sequential circuits -Behavioral modeling -Realization of Combinational and sequential circuits Switch-level modeling -
Realization of MOS circuits -Design using FSM -Realization of sequential circuits
Unit-2 - MOS Transistor 9 Hour
Generic overview of the MOS device: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion; nMOS transistor demonstrating cutoff, linear, and saturation regions of operation - Static
Conditions: The threshold voltage - Dynamic behavior: MOSFET Capacitances- Parasitic Resistances - Non-ideal I-V effects: Mobility Degradation, Velocity Saturation - Channel Length Modulation, Threshold
Voltage Effects - Leakage, Temperature Dependence, Geometry Dependence, Subthreshold Current-Short-channel MOSFETs: Hot carriers, LDD - MOSFET scaling - Short-channel effects: NBTI, oxide breakdown
- DIBL, GIDL, Gate Tunnel Current. CMOS Inverter Characteristics: Operation and properties of static CMOS inverter - Power Consumption - Dynamic Power Consumption, Total Power Consumption, PDP

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Unit-3 - VLSI Subsystem Design and Introduction to CMOS Logic Styles 9 Hour
Decoders -Comparators -Adders: Standard adder cells -Ripple Carry Adder (RCA) -Carry Look-Ahead Adder (CLA) -Carry Select /Save/skip Adder (CSL/CSA/ CSK). Multipliers: Overview of multiplication- types of
multiplier architectures -Braun multiplier -Baugh-Wooley multiplier -Wallace Tree multiplier -Booth multiplier CMOS Circuit Design Styles: Static CMOS logic styles -CMOS circuits, pseudo-nMOS, tristate circuits,
clocked CMOS circuits -DCVSL, Pass Transistor Logic (PTL) -Dynamic CMOS logic styles: NORA, TSPC
Unit-4 - Lithography and Relative Plasma Etching 9 Hour
Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Plasma properties, Feature Size control and Anisotropic Etch mechanism, reactive Plasma Etching techniques and Equipment.
Deposition, Diffusion, Ion implementation and Metallization Deposition process, Poly silicon, plasma assisted Deposition, Models of Diffusion in Solids, Fick’s one-dimensional Diffusion Equations – Atomic Diffusion
Mechanism – Measurement techniques – Range theory- Implant equipment. Annealing Shallow junctions – High energy implantation – Physical vapor deposition– Patterning.
Unit-5 - Process Simulation and VLSI Process Integration 9 Hour
Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching and Deposition- NMOS IC Technology – CMOS IC Technology – MOS Memory IC technology - Bipolar IC Technology – IC Fabrication -
NMOS.CMOS Fabrication processor flow- Analytical Beams – Beam Specimen interactions

1. S.M. Sze, “VLSI Technology”, McGraw Hill fourth Edition. 2008. 5. Digital Integrated Circuits: A Design Perspective", Pearson Education, 2015.
2. James D Plummer, Michael D. Deal, Peter B. Griffin, “Silicon VLSI Technology: 6. CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edison, Neil Weste, David Harris,
Learning
Fundamentals Practice and Modeling”, Prentice Hall India.2009. Pearson publication, 2015.
Resources
3. Wai Kai Chen, “VLSI Technology” CRC Press, 2013. 7. Douglas A. Pucknell, Kamran Eshraghian, "Basic VLSI Design, 3rd Edison, prentice Hall, 2016
4. Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolić,

Learning Assessment
Continuous Learning Assessment (CLA)
Summative
Formative Life-Long Learning
Bloom’s Final Examination
CLA-1 Average of unit test CLA-2
Level of Thinking (40% weightage)
(50%) (10%)
Theory Practice Theory Practice Theory Practice
Level 1 Remember 15% - 15% - 15% -
Level 2 Understand 25% - 20% - 25% -
Level 3 Apply 30% - 25% - 30% -
Level 4 Analyze 30% - 25% - 30% -
Level 5 Evaluate - - 10% - - -
Level 6 Create - - 5% - - -
Total 100 % 100 % 100 %

Course Designers
Experts from Industry Experts from Higher Technical Institutions Internal Experts
1. Mr. Saivineeth, ML Accelerator Architect@ Google 1. Dr. Meenakshi, Professor of ECE, CEG, Anna University, 1. Dr.J. Selvakumar, SRMIST
[email protected]
2. Mr. Anuj Kumar, Program Delivery Manager, Nagarro 2. Dr Venkatesan, Sr. Scientist, NIOT, Chennai, [email protected]
Software Pvt. Ltd. Gurgaon, [email protected]

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B.Tech / M.Tech (Integrated) Programmes-Regulations 2021-Volume-14-ECE-Higher Semester Syllabi-Control Copy