APSC 380 : I NTRODUCTION TO M ICROCOMPUTERS

1998/99 W INTER S ESSION T ERM 2

Microcomputer Architecture
This lecture gives an overview of the architecture of a simple microcomputer. It describes the operation of the CPU
address and data buses during read and write cycles.
After this lecture you should be able to: (1) show how the following buses and signals are connected in a micro-
computer system: power and ground, address and data buses, read and write strobes, and chip enables; (2) give the
sequence of signals that must appear on the address, data, and control lines of a memory or I/O chip in order to read
or write a particular data value to/from a particular address; (3) explain the purpose of these lines; and (4) compute
the number of address lines required for a given memory size or vice-versa.
Microcomputer Components EPROMs (erasable programmable read-only mem-
ory) which can be erased by exposing them to strong
A microcomputer is usually assembled from a micro- ultra-violet light for several minutes and then re-
processor chip (CPU1) connected to memory chips written using a device programmer. EEPROMs
and I/O (input/output) chips.

(electrically erasable programmable read-only mem-
CPU Memory I/O
ory) are similar to EPROMs, but individual addresses
can be erased (by writing to “magic” addresses) and

then re-written. “Flash” EEPROMs are similar, but
Address Bus
Data Bus


large parts of the device must be erased before they

can be re-written.
ROMs are used to store information that does not
Memories change. In an embedded system this might include
most of the software.
Memory chips store programs and data in micropro-
cessor systems. The two main types of memory chips
Read-Only Memory (RAM)
are ROMs and RAMs.
A RAM (random-access memory) is similar to a
ROM except that the values stored in the RAM can
Read-Only Memory (ROM)
be changed. The diagram below shows a typical
A ROM chip implements a lookup table. The input RAM chip:
to the ROM is called the “address” and the output is
address bus
called the “data.” A ROM can be configured (when data bus


it is manufactured or by using a “programming” de- output enable

RAM

vice) to generate a given value on its data output for R/W* (write strobe)
each address input.


Address ROM 

Data The address input selects the address that is to be

read or written.
Both the address input and the data output of a Unlike the ROM data bus, the RAM data bus is
ROM consists of multi-bit signals. “bi-directional:” it is an output (when the RAM is
Exercise: How wide is the address bus on a 64 kByte (216 being read) or an input (when the RAM is being writ-
byte) byte-wide (64ktimes8) ROM? How wide is the data bus? ten).
There are many types of ROM chips. The most There are also two control signals: “output en-
common are mask-programmed ROMs which come able” and “write strobe.” When the output enable
pre-programmed from the factory. There are also signal is asserted (true), data bus is an output and
the RAM acts like a ROM. When the write strobe is
1 Central Processing Unit asserted, the value on the data bus is stored in the

lec6.tex 1
 addressed memory location the case of the data bus, if it can alternate between
There are two main types of RAM chips. Static the two directions.
RAM (SRAM) chip storage their state in flip-flops


An address bus of N bits can be used to select (ad-

while dynamic (DRAM) chips store their state as the dress) one of 2N bytes in the microcomputer’s mem-
charge in a capacitor. This makes DRAM chips sim- ory. Typical address bus sizes (“widths”) are 16 bits
pler and cheaper than SRAM chips but DRAM mem- (most 8-bit microprocessors), 20 bits (the 8088 CPU
ory contents need to re-written (refreshed) every few used in the original IBM PC), 24 bits (the 68000 CPU
milliseconds since the change on the very small ca- used in the lab computer) and 32 bits (the chips used
pacitors decays with time. in modern microprocessors). The individual signals
Note that the contents of a RAM are lost when in the bus are usually given the labels A0 , A1 , A2 , . . . ,
power is removed. AN 1 .


Exercise: Is a RAM chip a combinational circuit or sequential

circuit? How about a ROM chip? Exercise: Approximately how many bytes can each of the
RAMs are used to store information that needs to above processors address? Hint: Use the approximation that
be changed. This includes variables and programs 210 is defined as “1k” and 220 is “1M.”
when they need to be loaded from external storage
The data bus is used to transfer data between mem-
such as disks.
ory or I/O peripherals and the CPU. The data bus
width in modern computers is always an even mul-
CPU tiple of 8 bits. For simplicity we will only consider
CPUs with an 8-bit data bus width. The individual
The following diagram shows the input and output signals in the data bus are usually given the labels
signals on a typical CPU: D0 , D1 , . . . , D7 .
power address bus The address and data buses connect the CPU to the
ground


data bus
memory and I/O chips. Multiple memory devices
clock


CPU can be connected in parallel to these buses but ad-

RD (read strobe)

ditional logic circuitry (“address decoders”) are re-
RESET WR (write strobe)
quired to ensure that only one device is enabled at a
time.
A signal is a voltage or current that transfers infor- Finally, there are a number of control signals. We
mation within a circuit. will only consider three of these: the read and write
As with any other digital logic chip, the CPU chip strobe outputs (RD and WR), and the RESET input.
needs pins to supply power and ground. The CPU
also needs a clock signal (a signal that periodically The RD and WR outputs are used to control mem-
switches from high to low). This clock input is used ory devices. If the RD output is high, the CPU is
by the processor to synchronize its internal opera- reading from memory (a “read” cycle); if the WR
tions. The processor is a (very complicated) state output is high the CPU is writing to memory (a
machine and the clock is used to sequence between “write” cycle). These signals are often active-low
the processor’s states. The clock speed typically (e.g. RD*) and/or are combined into two other sig-
ranges from 32768 (21 5) Hz to several hundred MHz. nals (R/W* and a data transfer strobe, DS*, signal).
A bus is a group of related signals. The CPU The RESET input pin resets the processor to a
has two buses: the address bus and the data bus. known initial state. This is usually done when power
These two buses are used by the processor to trans- is first applied or if the processor gets stuck while
fer instructions from memory chips to the CPU and executing a buggy program. When the RESET pin is
data between the CPU and memory or I/O chips. brought high the processor stops executing the cur-
The thick lines in the diagram above indicates the rent instruction sequence and restarts execution at an
buses carry multiple signals and the arrows indicate address that contains a program to restart the com-
whether the bus/signal is an input, output or, as in puter.

2
Read and Write Cycles the RAM detects the high signal on the WR line
and turns its data bus into an input
The following diagram shows the signals on a ROM
or RAM during a read cycle. the RAM stores the value currently on the data
1 next cycle

bus into the desired memory location inside the
Address Bus
RAM


4 5
Data Bus

Read Strobe 3 6 Exercise: Draw a timing diagram and write out a table similar
to those above showing the values appearing on the two strobes
The following operations take place during a read
and the address and data buses when the value 0x33 is written
operation (“cycle”):
to address 0x1200.

the CPU puts the address of the desired memory

location on the address bus (1)
I/O Chips
the CPU turns its data bus into an input (2)

the CPU asserts (brings high) the RD signal line I/O chips are used to allow the CPU to interface with
(3) peripherals (keyboards, printers, etc).
An output I/O chip consists of D flip-flops which
the RAM detects the high signal on the RD line are loaded during a write cycle. The flip-flops’ in-
and turns its data bus into an output (4) puts (D) are connected to the data bus and the outputs
the RAM looks up the value current value stored (Q) are connected to the peripheral. When the CPU
for that memory location and, after a short delay writes to the memory location that clocks the flip-
(the access time), outputs it on the data bus (5) flops, the flip-flops are loaded and the values written
to them remain on the output pins.
the CPU read the value from the memory (6) An input chip is simply buffer that causes the value
currently on the input pins to be transferred to the
The following table shows the values of the differ- CPU. This allows the CPU to monitor the state of the
ent signals over time during a read cycle where the input pins on the I/O chip.
CPU reads the value 0x32 from address 0x105:
The following diagram shows the internal struc-
address data RD WR ture of a simple parallel i/o chip:
bus bus Data Bus


D Q


0x105 X 0 0
0x105 X 1 0
decoder

Address Bus
0x105 0x32 1 0 

Write Strobe

The following operations take place during a write 

Data Bus
cycle:
decoder

Address Bus

the CPU puts the address of the desired memory Read Strobe
location on the address bus
There are many different I/O chips available. They
the CPU turns its data bus into an output usually include additional logic circuits to make it
easier for the CPU to deal with specific peripherals
the CPU puts the value to be stored on the data
such as modems or hard disks. Later in the course
bus
we will look at a few common interface chips.
the CPU asserts (brings high) the WR signal The following diagram shows the external inter-
line face of an i/o chip:

3
 power CPU, 64 bytes of RAM, 1kB of flash EEPROM for
ground
input pins
peripheral
program storage and 12 pins which can be used for
address bus I/O
I/O. Current microcontrollers range from 8-pin de-
output pins vices that sell for less than $1 to chips with hundreds
enable peripheral
RD (read strobe)
of pins that include Intel 486 processor ‘cores.’


WR (write strobe)

Address Decoders
A microcomputer often uses several memory and I/O
chips, each of which is smaller than the total amount
of memory that the microprocessor (CPU) can ad-
dress. For example, a CPU with with a 16-bit address
bus can address a 64 kBytes of memory but may be
used in a system with a 16 kByte RAM chip, a 32
kByte EPROM chip and a 4-byte I/O chip.
Exercise: How many address lines are required by each of
the above chips?
The purpose of the address decoder is to look at
the address output by the CPU and enable individual
memory or I/O chips. The following diagram shows
the inputs and outputs of an address decoder:
enable
power


Address enable
ground


Decoder
address bus enable

Exercise: Draw a diagram showing how a CPU with an 8-bit

data bus and a 20-bit address bus, two 8k by 8 RAMs, a 64k by
8 EPROM, an I/O chip with 4 internal one-byte ports and vari-
ous address decoders would be connected to build a microcom-
puter. Show the connections of the data and address buses and
the read and write strobes. Use arrows at each chip to indicate
whether a particular signal is an input or an output. Indicate the
width of each bus and the range of the address bus signals used
by each chip.

Microcontrollers
A microcontroller is a single-chip microcomputer.
The single chip includes the CPU, a RAM, an I/O
chip and an EPROM or EEPROM. This allows all of
the pins on the chip to be used for I/O. For example
the Atmel 89C1051 is a typical microcontroller. It is
a 20-pin chip which contains a clone of an Intel 8051