Power plan

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Power plan

Power planning is done to provide uniform supply voltages to all cells in the design. The primary objec ve of
power planning is to ensure that all on chip components (blocks, memory, I/O cells etc...) have adequate
power and ground connec ons. Three levels of Power Distribu on:

1. Rings - Carries VDD and VSS around the chip

2. Stripes - Carries VDD and VSS from Rings across the chip

3. Rails - Connect VDD and VSS to the standard cell VDD and VSS

Core Power Management:

VDD and VSS power rings are formed around the core and macro. In addi on to this straps and trunks are
created for macros as per the power requirement. Std cell rails are created to tap power from power straps to
std cell power/ground pins.

I/O Power Management:

Power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.

Inputs of Power plan:

- Netlist & SDC

- .lib , .lef & tech file

- Tlu+ file

- UPF
UPF Contents:

Power intent specifies:

Power Distribu on Architecture:

- Power domains – Group of elements which share a common set of power supply requirements

- Supply rails – Power distribu on (ports, nets, sets & switches)

- Shutdown control

Power Strategy:

- Power state tables – Legal combina on of states of each power domain

- Opera ng voltages

Usage of Special cells:

- Isola on cells

- Level shi ers

- Power switches

- Reten on registers

Isola on Cells:

- Powered off domains do not drive their outputs anymore and these outputs become floa ng nodes. This
could be a problem when other ac ve domains gets these floa ng nodes as input. It could result in crowbar
current which affects the proper func oning of the powered up domain.
 - Isola on cells (also called “clamps”) keep the turned off sub-block outputs at a predefined value. This is how
the shut-down sub-block does not corrupt other ac ve sub-block func onality.

- Isola on cells are powered by a constant supply and drive 0, 1 or latch the old value of the turned off
domain.

- Isola on cells pass logic values during the normal mode of opera on, but clamp it to some specified value
when a control signal is asserted.

- Isola on cell clamps the output of powered down block to a specified value (‘0’, ‘1’, last)

- Gate type clamp cells (AND, OR)

- Transistor type clamp (pull-up, pull-down)

- Level shi ers have the minimal func onality of a buffer.

- Necessary as most low-power designs have mul -voltage domains and/or employ dynamic voltage scaling.

- A level shi er swings a logic value in one voltage domain to the same logic value in another voltage domain.

- An ‘Up’ level shi er swings a logic value from a lower voltage domain to the same logic value in a higher
voltage domain.

- A ‘Down’ level shi er swings a logic value from a higher voltage domain to the same logic value in a lower
voltage domain.

Reten on Registers:

- In order to reduce power consump on, memories are shut down where their power domain is switched off
or when they are not in use. Registers are corrupted when power is switched off. Corrup on is typically
represented as ‘X’ (unknown).

- Some memories need to retain their values for fast wake-up. For these memories, only the memory array
stays powered on during the shut-down while the peripheral interfaces are powered off.

- Reten on registers keep their previous ac ve value a er being shut down.

- Reten on registers save state informa on before a power domain is switched off and restore it when the
power is turned back on.
 - Reten on registers comprise of two circuits.

- Standard register logic, supplied by primary power VDD

- Shadow latch reten on circuitry, with alternate supply VDDB

- SAVE – transfers FF content into shadow latch during shutdown

- RESTORE – transfers state from shadow latch to FF when powered back on

Frequently Used Power Reduc on Techniques:

Power Ga ng:

- In a processor chip, certain areas of the chip will be idle and will be ac vated only for certain opera ons. But
these areas are s ll provided with power for biasing.

- The power ga ng limits this unnecessary power being wasted by shu ng down power for that area and
resuming whenever needed.

- It is used for reducing LEAKAGE POWER or power consump on by switching off power supply to the non
opera onal power domain of the chip during certain mode of opera on.
 - Header & footer switches, isola on cells, state reten on flip flops are used for implemen ng power ga ng.

Clock Ga ng:

- Clock ga ng limits the clock from being given to every register or flops in the processor. It disables the clock
of an unused device. In clock ga ng the gated areas will s ll be provided with bias power.

- It is used for reducing DYNAMIC POWER by controlling switching ac vi es on the clock path.

- Generally gate or latch or flip flop based block ga ng cells are used for implemen ng clock ga ng.

- 50% of dynamic power is due to clock buffer. Since clock has highest toggle rate and o en have higher drive
strength to minimize clock delay. And the flops receive clocks dissipates some dynamic power even if input and
output remains the same. Also clock buffer tree consumes power. One of the techniques to lower the dynamic
power is clock ga ng.

- In load enabled flops, the output of the flops switches only when the enable is on. But clock switches
con nuously, increasing the dynamic power consump on.

- By conver ng load enable circuits to clock ga ng circuit dynamic power can be reduced. Normal clock ga ng
circuit consists of an AND gate in the clock path with one input as enable. But when enable becomes one in
between posi ve level of the clock a glitch is obtained.
 - To remove the glitches due to AND gate, integrated clock gate is used. It has a nega ve triggered latch and an
AND gate.

- Clock ga ng makes design more complex. Timing and CG ming closure becomes complex. Clock ga ng adds
more gates to the design. Hence min bit width (minimum register bit width to be clock gated) should be wisely
chosen, because the overall dynamic power consump on may increase.

Voltage and Frequency Scaling:

- It changes the voltage and clock frequency to match the performance requirements for a given opera on so
as to minimize leakage.

- Different blocks are operated at variable supply voltages. The block voltage is dynamically adjusted based on
performance requirements.

- Frequency of the block is dynamically adjusted. Works alongside with voltage scaling.

Substrate Biasing:

- It changes the threshold voltage to reduce leakage current at the expense of slower switching mes.

Mul ple Threshold Voltages:

- Uses different Vt in the circuit to reduce leakage but s ll sa sfy ming constraints.
Mul ple Supply Voltages:

- Using Mul VDD reduces power consump on by powering down the not used voltage domain. Different
blocks are operated at different supply voltages. Signals that cross voltage domain boundaries have to be level
shi ed.

Memory Par oning:

- The memory is split into several par ons. Not used ones can be powered down.

Types of Power Dissipa on:

The power dissipa on is classified in two categories:

- Sta c power dissipa on

- Dynamic power dissipa on

Sta c Power Dissipa on:

In this class, power will be dissipated irrespec ve of frequency and switching of the system. It is con nuous and
has become more dominant at lower node technologies. The structure and size of the device results in various
leakage currents. Few reasons for sta c power dissipa on are:

- Sub-threshold current

- Gate oxide leakage

- Diode reverse bias current

- Gate induced leakage

Its hard to find the accurate amount of leakage currents but it mainly depends on supply voltage (VDD),
threshold voltage (Vth), transistor size (W/L) and the doping concentra on.
Dynamic Power Dissipa on:

There are two reasons of dynamic power dissipa on; Switching of the device and short circuit path from supply
(VDD) to ground (VSS). This occurs during opera on of the device. Signals change their logic state charging and
discharging of output mode capacitor.

Short-circuit Power Dissipa on:

Because of slower input transi on, there will be certain dura on of me “t”, for which both the devices (PMOS
and NMOS) are turned ON. Now, there is a short circuit path from VDD to VSS. This short circuit power is given
by:

Pshort-circuit = Vdd. Isc. t

where, Vdd – Supply voltage, Isc – Short-circuit current and t – Short-circuit me.

Short-circuit power is directly propor onal to rise me and fall me.

Switching Power Dissipa on:

Energy is drawn from the power supply to charge up the output mode capacitance. Charging up of the output
cap causes transi on from 0V to VDD. So, the power dissipated during charging and discharging of total load
[output capacitance + net capacitance + input capacitance of driven cell(s)] is called Switching power
dissipa on. The switching power is given by:

Pswitch = α·VDD2 · Cload·f

where, α – Switching ac vity factor, f – Opera ng frequency,

VDD – Supply voltage & Cload – Load capacitance.