Mapping function: The cache memory can store a reasonable number of blocks at any given

time, but this number is small compared to the total number of blocks in the main memory. Thus
we have to use mapping functions to relate the main memory blocks and cache blocks. There are
two mapping functions commonly used direct mapping and associative mapping. Detail
description of mapping functions is given in section 8.4.6.

Replacement algorithm: When a new block is brought into the cache, one of the existing blocks
must be replaced, by a new block.

• There are four most common replacement algorithms:

• Least-Recently-Used (LRU)

• First-In-First-Out (FIFO)

• Least-Frequently-Used (LFU)

• Random

• Cache design change according to the choice of replacement algorithm. Detail description of
replacement algorithm is given in section 8.4.8.

Write policy: It is also known as cache updating policy. In cache system, two copies of the same
data can exist at a time, one in cache and one in main memory. If one copy is altered and other is
not, two different sets of data become associated with the same address. To prevent this, the
cache system has updating systems such as: write through system, buffered write through system
and write-back system. The choice of cache write policy also change the design of cache.

Block size: It should be optimum for cache memory system.

Number of caches: When on-chip cache is insufficient, the secondary cache is used. The cache
design changes as number of caches used in the system changes.

Mapping

• Usually, the cache memory can store a reasonable number of memory blocks at any given time,
but this number is small compared to the total number of blocks in the main memory. The
correspondence between the main memory blocks and those in the cache is specified by a
mapping function.

• The mapping techniques are classified as :

1. Direct-mapping technique

2. Associative-mapping technique
• Fully-associative

• Set-associative techniques.

• To discuss these techniques of cache mapping we consider a cache consists of 128 blocks of 16
words each, for a total of 2048 (2 K) words and assume that the main memory has 64 K words.
This 64 K words of main memory is addressable by a 16-bit address and it can be viewed as 4 K
blocks of 16 words each. The group of 128 blocks of 16 words each in main memory form a
page.

Direct-Mapping

• It is the simplest mapping technique.

• In this technique, each block from the main memory has only one possible location in the cache
organization. In this example, the block i of the main memory maps onto block j(j = i modulo
128) of the cache, as shown in Fig. 8.4.6. Therefore, whenever one of the main memory blocks 0,
128, 256, ...... is loaded in are stored in cache, it is stored in cache block 0. Blocks 1, 129, 257,
…… block 1 and so on.

In general the mapping expression is

j = i modulo m

where

i =Main memory block number

j=Cache block (line) number

m= Number of blocks (lines) in the cache

• To implement such cache system, the address is divided into three fields, as shown in Fig.
8.4.6.

• The lower order 4-bits select one of the 16 words in a block. This field is known as word field.

• The second field known as block field is used to distinguish a block from other blocks. Its
length is 7-bits since 27 = 128.

• When a new block enters the cache, the 7-bit cache block field determines the cache position in
which this block must be stored.

• The third field is a tag field. It is used to store the high-order 5-bits of memory address of the
block. These 5-bit (tag bits) are used to identify which of the 32 blocks (pages) that are mapped
into the cache.
• When memory is accessed, the 7-bit cache block field of each address generated by CPU points
to a particular block locationin the cache. The high-order 5-bits of the address are compared with
the tag bits associated with that cache location. If they match, then the desired word is in that
block of the cache. If there is no match, then the block containing the required word must first be
read from the main memory and loaded into the cache.

• This means that to determine whether requested word is in the cache, only tag field is necessary
to be compared. This needs only one comparison.

• The main drawback of direct mapped cache is that if processor needs to access same memory
locations from two different pages of the main memory frequently, the controller has to access
main memory frequently. Since only one of these locations can be in the cache at a time. For
example, if processor want to access memory location 100 H from page 0 and then from page 2,
the cache controller has to access page 2 of the main memory. Therefore, we can say that direct-
mapped cache is easy to implement, however, it is not very flexible.

Associative-Mapping (Fully-Associative Mapping)

• The Fig. 8.4.7 shows the associative-mapping technique. In this technique, a main memory
block can be placed into any cache block position. As there is no fix block, the memory address
has only two fields: word and tag. This techniques is also referred to as fully-associative cache.

• The 12-tag bits are required to identify a memory block when it is resident in the cache. The
high-order 12-bits of an address received from the CPU are compared to the tag bits of each
block of the cache to see if the desired block is present.

• Once the desired block is present, the 4-bit word is used to identify the necessary word from the
cache.

• This technique gives complete freedom in choosing the cache location in which to place the
memory block. Thus, the memory space in the cache can be used more efficiently.

• A new block that has to be loaded into the cache has to replace (remove) an existing block only
if the cache is full.

• In such situations, it is necessary to use one of the possible replacement algorithm to select the
block to be replaced.

• Disadvantage:In associative-mapped cache, it is necessary to compare the higher-order bits of

address of the main memory with all 128 tag corresponding to each block to determine whether a
given block is in the cache. This is the main disadvantage of associative-mapped cache.

Set-Associative Mapping
• The set-associative mapping is a of both direct and associative mapping.

• It contains several groups of direct-mapped blocks that operate as several direct-mapped caches
in parallel.

• A block of data from any page in the main memory can go into a particular block location of
any direct-mapped cache. Hence the contention problem of the direct-mapped technique is eased
by having a few choices for block placement.

• The required address comparisons depend on the number of direct-mapped caches in the cache
system. These comparisons are always less than the comparisons required in the fully-associative
mapping.

• Fig. 8.4.8 shows two way set-associative cache. Each page in the main memory is organized in
such a way that the size of each page is same as the size of one directly mapped cache. It is
called two-way set-associative cache because each block from main memory has two choices for
block placement.
• In this technique, block 0, 64, 128,.....4032 of main memory can map into any of the two (block
0) blocks of set 0, block 1, 65, 129,,...., 4033 of main memory can map into any of the two (block
1) blocks of set 1 and so on.

• As there are two choices, it is necessary to compare address of memory with the tag bits of
corresponding two block locations of particular set. Thus for two-way set-associative cache, we
require two comparisons to determine whether a given block is in the cache.

• Since there are two direct-mapped caches, any two bytes having same offset from different
pages can be in the cache at a time. This improves the hit rate of the cache system.

• To implement set-associative cache system, the address is divided into three fields, as shown in
Fig. 8.4.8.

• The 4-bit word field selects one of the 16 words in a block.

• The set field needs 6-bits to determine the desired block from 64 sets. However, there are now
64 pages. To identify a block belongs to a particular page from 64 pages, six tag bits are required.

Example 8.4.2 Consider a cache consisting of 256 blocks of 16 words each, for a total of 4096
(4 K) words and assume that the main memory is addressable by a 16-bit address and it consists
of 4 K blocks. How many bits are there in each of the TAG, BLOCK/SET and word fields for
different mapping techniques ?

Solution: We know that memory address is divided into three fields. We will now find the exact
bits required for each field in different mapping techniques.

a) Direct-mapping

Word bits: We know that each block consists of 16 words. Therefore, to identify each word we
must have (24 = 16) four bit reserved for it.

Block bits: The cache memory consists of 256 blocks and using direct-mapped technique, block
k of the main memory maps onto block k modulo 256 of the cache. It has one to one
correspondence and requires unique address for each block. To address 128 block we require
(28 = 256) eight bits.

Tag bits: The remaining 4 (16 – 4 - 8) address bits are tag bits which stores the higher address of
the main memory.

The main memory address for direct-mapping technique is divided as shown below:
b) Associative-mapping

Word bits: The word length will remain same i.e. 4 bits.

In the associative-mapping technique, each block in the main memory is identified by the tag bits
and an address received from the CPU is compared with the tag bits of each block of the cache to
see if the desired block is present. Therefore, this type of technique does not have block bits, but
all remaining bits (except word bits) are reserved as tag bits.

Block bits: 0

Tag bits: To address each block in the main memory (212 = 4096) 12 bits are required and
therefore, there are 12 tag bits.

The main memory address for direct mapping technique is divided as shown below:

c) Set-associative mapping

Let us assume that there is a 2-way set-associative mapping. Here, cache memory 'is mapped
with two blocks per set. The set field of the address determines which set of the cache might
contain the desired block.

Word bits: The word length will remain same i.e. 4 bits.

Set bits: There are 128 sets (256/2). To identify each set (27 = 128) seven bits are required.

Tag bits: The remaining 5 (16 – 4-7) address bits are the tag bits which stores higher address of
the main memory.

The main memory address for 2-way set associative mapping technique is divided as shown
below:
 (OR)

1. Mapping Techniques

Mapping techniques are methods used to map data from one memory location to another,
typically from the main memory to the cache memory or from virtual memory to physical
memory. The goal of mapping is to optimize the speed of data retrieval while maintaining data
consistency and integrity.

There are three primary types of cache mapping techniques used to map data from main
memory to cache memory:

a) Direct-Mapped Mapping:

In direct-mapped mapping, each block of main memory is mapped to exactly one cache line.
This means that a specific block of data in main memory will always map to a specific cache
line.

 Process: The address is divided into two parts: the index and the tag. The index
identifies the cache line where the block will be stored, and the tag is used to identify
which block is currently stored in that cache line.
 Advantages: Simple to implement and quick lookup.
 Disadvantages: High possibility of cache misses if multiple memory blocks map to the
same cache line (known as cache conflict).

b) Fully Associative Mapping:

In fully associative mapping, any block of main memory can be stored in any cache line. This
gives more flexibility in where data can be placed in the cache.

 Process: The entire memory address is used as the tag, and the cache has a search
process to find which block is currently stored in the cache.
 Advantages: Minimizes cache misses as data can be stored anywhere in the cache.
 Disadvantages: More complex and slower lookup process due to the need to search
through all cache lines for a match.

c) Set-Associative Mapping:
Set-associative mapping is a compromise between direct-mapped and fully-associative
mapping. In this method, the cache is divided into several sets, and each memory block can be
mapped to any cache line within one set.

 Process: The memory address is divided into three parts: the set index, the tag, and the
block offset. The set index identifies which set the block belongs to, and the cache line
within that set can be chosen to store the block.
 Advantages: Provides a balance between flexibility and complexity, reducing the
possibility of conflict misses while keeping the lookup time manageable.
 Disadvantages: Slightly more complex than direct-mapped, but less so than fully-
associative.

2. Replacement Techniques

When the cache or memory is full, the system needs to decide which data to remove (replace) in
order to make room for new data. Replacement techniques are essential in cache memory
management. There are several common algorithms used to decide which block to evict when a
cache miss occurs.

a) Least Recently Used (LRU):

The LRU replacement algorithm evicts the block that has not been used for the longest period of
time.

 Process: Every time a block is accessed, its reference time or position in a queue is
updated. When a replacement is needed, the block with the oldest reference time is
evicted.
 Advantages: Provides a good approximation of the optimal replacement policy (which
evicts the least likely to be used block).
 Disadvantages: Implementing LRU can be resource-intensive because it requires
tracking the order of block usage, which may involve maintaining counters or stacks.

b) First-In, First-Out (FIFO):

The FIFO algorithm replaces the oldest block in the cache, regardless of how frequently or
recently it has been accessed.

 Process: The blocks are arranged in a queue, and when a new block is brought into the
cache, it is added to the end of the queue. The block at the front of the queue (the oldest
one) is evicted when necessary.
 Advantages: Simple to implement.
 Disadvantages: It does not always make the best decision, as the oldest block may still
be needed frequently.

c) Optimal (OPT) or Belady’s Algorithm:

The optimal replacement strategy replaces the block that will not be used for the longest period
of time in the future. This is the ideal algorithm, as it minimizes cache misses.

 Process: The algorithm looks ahead and chooses to replace the block that will not be
used for the longest duration, which is the most "optimal" choice.
 Advantages: It guarantees the lowest number of cache misses.
 Disadvantages: It is impractical in real systems because it requires knowledge of future
memory accesses, which is usually not available.

d) Least Frequently Used (LFU):

The LFU algorithm replaces the block that has been accessed the fewest times. This strategy
assumes that blocks with fewer accesses are less likely to be needed in the future.

 Process: A counter is maintained for each cache block that increments every time the
block is accessed. When replacement is necessary, the block with the smallest counter
value is replaced.
 Advantages: Good for caches where some data is accessed frequently, and others are
used rarely.
 Disadvantages: Can be inefficient in dynamic scenarios where the access pattern
changes frequently.

e) Random Replacement:

The random replacement algorithm selects a cache block at random to evict when space is
needed for new data.

 Process: The system randomly selects a cache line and evicts it to make space for the
new block.
 Advantages: Simple to implement and requires very little overhead.
 Disadvantages: It can perform poorly in terms of cache miss rates compared to more
sophisticated algorithms like LRU or LFU.