STUDENT

GATE I
T VLSI

Ph
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1.Introduc tiont oVLSI 1.Intr

oduc tiont oVe r
ilog 1.Introduc tiont oVLSI 1.Bas icCi rc uitThe ory 1.LayoutDe signRul es
2.Introduc tiont oLi nux 2.DataTy pesandOpe r ator s 2.Introduc tiont oLi nux 2.Se mic onduc torDe vices 2.Transist
orSi zingandSc al i
ng
3.Advanc edDi gitalDe sign 3.Combi nationalLogi cDe si
gn 3.Advanc edDi git
alDe sign (Trans istor s,Diode s) 3.Acti
veandPas siveDe vi
ceLay out
4.VerilogHDL-RTLCodi ng&Sy nthesi
s 4.Seque nti
alLogi cDe s ign 4.StaticTimi ngAnal ys
is 3.Ope rat i
onalAmpl if
ie r
s( Op-Amps ) 4.Parasiti
cCapac i
tanc e,Induc tance,and
5.StaticTimi ngAnal y s
is 5.StateMac hi nes 5.FPGAAr c hite c
tur e 4.Anal ogF ilte rs(Low- pass,Hi gh-pas s, Re si
stanc e
6.FPGAAr c hite ct
ur e 6.Procedur alBl ocks( alway s,i
ni t
ial) 6.VerilogHDL- RTLCodi ng&Sy nt
hes
is Band- pas s ,Band- stop) 5.DeviceMat chingandDi fferent i
alPairs
7.CodeCov er age 7.TaskandF unc t
ion 7.CMOSF undame ntals 5.Bi asingandSt abilizati
onTe chni ques 6.CurrentMi rrorsandBi asingNe t
wor ks
8.VerilogMi niPr ojectRTLCodi ng& 8.De l
aysandTi mi ngCont r
ols 8.De signAut omat ionus i
ng 6.Di ff
er enti
alAmpl i
fiers 7.Powe randGr oundDi st
ribution
Sy nthes is 9.Testbenche sandSi mul ati
on Sc ripts-Pe rl 7.Fe edbac kandSt abilit
y 8.LayoutforNoi s eI mmuni t
y
9.CMOSF undame ntals 10.Finit
eSt at eMac hine( FSM)De s i
gn 9.CodeCov er age 8.Noi seandSi gnalI ntegrity 9.Elect
romagne ticInt erf
er ence( EMI)
10.De signAut omat i
onus ingSc riptsPerl 11.De si
gnHi erarchyandModul arit
y 10.Ve ril
ogMi niPr ojectRTLCodi ng& 9.Anal og-to-Di git
al&Di git
al-to-Anal og Cons iderati
ons
11.ASI CVe rif
ic ationMe thodol ogies 12.VerilogforF PGADe s ign Sy nthes i
s Conv e rs
ion 10.ThermalManage me nt
12.Sy stemVe rilogHVL 13.Synthe si
sandI mple me ntat
ion 11.De s i
gnf orTe stabil
ity-DF T 10.Os c il
lator sandSi gnalGe ne rator s 11.LayoutVe rifi
c ati
onandDRC
13.Adv anc edSy stemVe rilog 14.VerilogforASI CDe s ign 12.DF TPi lotPr oject 11.Powe rAmpl if
iers (De si
gnRul eChe cking)
14.UVM -Uni ve rsalVe rifi
c ati
on 15.Sys t
e mVe ril
ogEx tens ions 13.RI SCVPr oc essor 12.F reque nc yRe spons eandBandwi dt
h 12.LVS( Layoutv s .Sc hemat ic)Ve r
ifi
cati
on
Me thodol ogy 16.UVM 14.Bus i
ne ssc ommuni cation 13.I mpe danc eMat ching 13.Paras i
ticEx t
rac ti
onandSi mul ati
on
15.Ve rif
icationMi niPr oje ct 17.STA 15.Indus trySt andar dPr oject 14.Ac tiveandPas si
veCompone nts 14.FloorplanningandRout ing
16.Inte r
fac esandPr otoc ols 16.Inte r
fac esandPr otoc ols 15.Anal ogDe signf orMi xed-Signal 15.Layoutf orHi gh-Spe edAnal ogCircuit
s
17.Ve rif
icationPl anning&Manage ment Sy s
te ms
18.As sertionBas e dVe rif
ic at
ion-SVA 16.Si mul ationandDe si
gnTool s( SPICE,
19.Bus ine ssc ommuni cation Cade nce ,etc.)
20.RI SC-VPr oc es sor
21.Indus trySt andar dPr oje c
t
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