Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)

IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

A High Speed Flash Analog to Digital Converter

K.Sai Kumar, K.Lokesh Krishna, K. Sampath Raghavendra K.Harish
ECE Department ECE Department ECE Department ECE Department
S.V. College of S.V. College of S. V. College of S. V. College of
Engg.,Tirupati, Engg.,Tirupati, Engg.,Tirupati, Engg.,Tirupati,
Andhra Pradesh. Andhra Pradesh. Andhra Pradesh. Andhra Pradesh.
[email protected]

Abstract— This paper presents the design and Pipelined, Sigma-Delta, Flash type, Folding, Sub ranging, and
implementation of a 4-b Flash Analog to Digital Converter Interleaved techniques are being used to achieve this
(ADC) in 180nm digital CMOS technology. The proposed flash specifications [1]. Of these, Flash ADC architecture has been
ADC utilizes resistive ladder logic network, high speed demonstrated to be the most efficient for applications such as
comparators and a encoder logic to convert the given continuous Ultra Wideband (UWB) Communication systems, digital
input signal into output binary code. The flash ADC utilizes a storage oscilloscopes, high speed data acquisition systems,
novel encoder realized using pseudo dynamic CMOS logic which high quality video processing systems, Blu-Ray or DVD
has been implemented with fewer transistors compared to the readouts, remote sensing, and space probes. The quick
previous other techniques. Without the need of time interleaving
advances in these application areas is encouraging the circuit
technique, the proposed ADC is capable of operating at its full
sampling rate. The designed flash ADC consumes 0.686mW when
designers to design ADCs to operate at higher operating
operated from a power supply voltage of 1.8V. The operating speeds, consume lower power consumption, better resolution
speed of this circuit is 10GHz and the simulated integral non- and smaller die size. The comparison of various ADC
linearity error (INL) and differential non-linearity error (DNL) architectures is presented in figure 1. Sigma-Delta architecture
are between 0.1/-0.02LSB and 0.33/-0.12LSB respectively. It operates with highest resolution but at lesser speeds.
occupies an effective area of 0.32mm2. Successive Approximation Register (SAR) type ADCs
operates at medium resolution and speed.
Keywords—Low voltage, High speed, Time interleaving,
Sample and Hold circuit, Low power, Inverter, Least Significant
Bit, Most Significant Bit, Comparator and CMOS.

I. INTRODUCTION

In recent years there has been rapid progresses in the

development of digital computing and signal processing in the
design and implementation of numerous electrical and
electronic systems. The importance of data converters in the
implementation of signal processing and digital computing in
image processing, wireless communications, industrial
instrumentation circuits and various industrial control systems
is increasing by leaps and limits. At present the key
innovations in consumer electronics systems are reflected in
laptops, smart phones, camcorders, tablets and various
portable storage devices. One of the key components in all the
above mentioned devices is the ADC, which acts as periphery
between analog and digital domains.
An ADC is a mixed signal device that changes the given
continuous input signal into digital output signal. For various
System-on-Chip (SoC) applications, which often aim portable
applications require high resolution, very high speed, and low
power ADCs. High resolution, high speed and ultra-low power
of the order of microwatts are the important requirements in
numerous wireless receiver system applications. To achieve
these important specifications, various ADC architectures are
available. Based on the application, architectures such as Fig. 1. Comparison of various ADC architectures

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 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

bits, (2N-1) numbers of comparator circuits are required. The

derived reference voltage (Vref) for each comparator is atleast
Presently flash analog to digital converter (ADC)
architectures are the best selection for use in various wireless one least significant bit (LSB) higher than the reference
board to board communications in super computers, ultra-high voltage for the comparator circuit next underneath it. The
speed applications such as UWB communication systems, comparator produces logic high output voltage when its
portable products, and digital storage oscilloscopes etc. M. El- analog input voltage exceeds the reference voltage applied to
Chamma et al. [2] presented a 12GS/s 5-bit time-interleaved it. Otherwise, a logic low is produced at the output of
flash ADC realized in 65nm CMOS. In this work power comparator circuit.
consumption is minimized by employing minimum size
comparators. P. Ritter et al. [3] presented a novel comparator
circuit scheme and reference ladder concept for the design of
flash ADC that reduces dynamic reference voltage (Vref)
distortions at high signal speed. C. H. Chan et al. [4] presented
a 5bit 1.25GS/s folding flash ADC. The prototype ADC
fabricated using 65nm digital CMOS technology show that it
operates with very low power consumption and yields a figure
of merit of 17fJ/conversion step. B. Verbruggen et al. [5]
presented a folding flash ADC, in which number of
comparators has reduced drastically, thereby reducing power
consumption and die size. S. Park et al. [9] presented a
designed 4-bit non-interleaved flash ADC in 180nm digital
CMOS. It operates at a sampling speed of 4GS/s and the
measured INL and DNL were shown as 0.24LSB and
0.15LSB. C. Huang et al. [10] presented a fabricated 8-
channel, 6 bit 16GS/s time-interleaved (TI) ADC. Comparator
circuits are designed without the use of preamplifiers. Also
current ADC designs in nanometer scale lengths CMOS
technologies encounter numerous limitations such as reduced
amplifier gain, high offset voltage, inadequate voltage
headroom, and mismatches in transistors and switch linearity
degradation. The sampling frequency of a flash ADC is
limited by the comparator delay. So by properly designing the
comparator, delay can be reduced and sampling frequency can
be improved significantly. In this proposed paper a high speed
flash ADC is designed and implemented in 180nm CMOS
technology.
The paper is prepared as follows. Section II discusses the
design of proposed 4-bit flash ADC architecture. It also
presents the inner blocks of the flash ADC. While section III
presents the implementation of overall ADC architecture.
Section IV contains simulated results of the 4-bit flash ADC
and Section V gives the conclusions.

II. FLASH ADC ARCHITECTURE Fig. 2. Architecture of 4-bit Flash ADC

The point where the binary code varies from ones to zeros is
Flash ADC, also recognized as parallel ADCs. They are the the point where the input signal becomes smaller than the
fastest data converters to transform a given input analog signal respective comparator fixed reference voltage levels. This type
to a output digital data. However the main disadvantage of of coding is recognized as thermometer code encoding
these flash ADCs is that they have relatively low resolution scheme, so called since it is very much similar to general
and circuit complexity is high which in turn occupies larger mercury based thermometer, wherein the mercury reading in
chip area. Figure 2, shows the complete schematic diagram of the instrument continually rises to the appropriate temperature
the proposed 4bit flash ADC architecture. and no mercury reading is present beyond that temperature.
Finally the generated thermometer digital code is then
Flash analog to digital converters are constructed by translated to get the suitable N-bit digital output bits. A
cascading comparator circuits. It consists of a resistive divider sample and hold circuit (S/H) is connected at the front end
network with 2N number of resistors (N denotes number of stage of the flash ADC to sample and hold the value and pass
bits), which provides the fixed reference voltage to each input it to the comparator. The parallel structure ensures a high
side of the comparator. For a flash converter with N number of operation speed and minimized conversion delay.

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IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

There are different kinds of comparator architectures such as

In this proposed paper, a novel four bit flash ADC is designed clock based dynamic comparator, clock based double tail
and implemented, which consists of sixteen resistors of fixed comparator, continuous time comparator, threshold inverted
value, generating fifteen different reference voltages for quantization (TIQ) based comparator and standard cell based
comparators. The output of comparator circuits are a fifteen comparator. In the proposed two step flash ADC, a modified
bit thermometric code, which is then properly encoded to get double tail comparator circuit is used. The working of
final four bit digital output data using an encoder. operation is explained as follows: During the reset stage of
operation i.e. when CLK=0, both transistors TT1 and TT2 are
off. So T4 and T3 pull both Fp and Fn nodes to power supply
A. Sample and Hold (S/H) circuit:
voltage VDD. Hence transistors TC2 and TC1 are switched off.
The intermediate stage consisting of transistors T R1 and TR2
resets both latch outputs to ground. Similarly during decision
making phase i.e. when CLK=VDD, both transistors TT1 and
TT2 are switched on. At the commencement of this decision
making phase, both the transistors are still cut off. Thus Fn and
Fp jump to fall with changed rates according to the input signal
voltages.

Fig. 3. Schematic circuit diagram of S/Hold circuit

The S/H circuit is a very fundamental and important analog

circuit block in many wireless communication circuits. The
circuit diagram of S/H circuit is presented in figure 3. An S/H
circuit is to sample the applied input signal and clamp the
obtained value over a definite period of time for sub sequent
processing. The S/H circuit is used in ADC to reduce
deviations in input signal that can override the conversion
process. Here the transmission gate controls the electrical
connection between input and output of the circuit. During the
sample phase, the transistor acts as a short circuit and the
impedance between the input and output depends on the drain
to source resistance of the transistor. A sine wave of amplitude
of 1Vp-p is given at the input of S/H circuit. The circuit is
operated from a dc power supply voltage of ±1.8V, and clock
frequency is 10GHz.

B. Comparator circuit:

Comparator circuits designed implemented using CMOS

technologies are the most vital basic building blocks in analog
and mixed-mode circuit designs. The circuit diagram of
comparator circuit is presented in figure 4.
Fig. 4. Schematic diagram of comparator circuit
A CMOS comparator circuit compares the given
analog signal with a valid reference signal (Vref) and generates C. Thermometer code to Output binary code circuit:
a binary signal output. In this proposed work the design of
The comparator circuit produces output containing ones and
comparator plays a major role in high speed conversion [6].
zeros and can be visualized as a thermometer code. This

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 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

thermometric code is then decoded to get the proper digital number of transistors required for the conversion from
output code. Various designs are available for decoding the thermometric code to output digital code is 46.
thermometer code such as programmable logic array (PLA)
decoding technique, read only memory (ROM) decoding
technique, XOR encoder, Fat tree encoder and Wallace tree
encoder etc. [7]-[8]. In this proposed flash ADC, the design
and implementation of encoder circuit is carried out using
pseudo dynamic CMOS logic. This pseudo dynamic CMOS
logic technique significantly reduces the number of MOS
transistors in the design, thereby increasing the speed of
operation and consumes less power. The proposed design
utilizes the AND-OR-Invert (AOI) gates. The key benefit of
this method is that the thermometric code is directly changed
to binary output code without using any intermediate
conversion method. The designed expressions for various
output digital bits are

Fig. 5. Schematic diagram of bit B0

where bits B3, B2, B1, B0 are output digital bits and M0, M1,
M2, M3.......……M15 are outputs of comparators.

In a MOS transistor at cutoff, for a gate to source voltage and

threshold voltage,VGS < Vth; drain current (IDS) =0. In linear or
triode region, for VGS > Vth; and VDS < (VGS-Vth), the
expression for drain current is given by
Fig. 6. Schematic diagram of bit B1

In saturation region, for VGS> Vth; and VDS > (VGS-Vth), the
expression for drain current is given by

In weak inversion, for VGS≡ Vth; and VDS >0V, the expression
for drain current is given by

The transistorized schematic diagram for generation of bits B0,

B1 and B2 are shown in the figure 5, 6 and 7. The total Fig. 7. Schematic diagram of bit B2

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IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

III. IMPLEMENTATION OF FINAL ADC ARCHITECTURE

All the fifteen comparators, thermometric code to output
binary code logic circuit and sample and hold circuit were
integrated and the final schematic diagram is presented in the
figure 8. The logic diagram of 4bit flash ADC is modeled
using Virtuoso and simulated using Cadence Spectre.

Fig. 9. Simulation results of Flash ADC

Fig. 8. Final logic diagram of 4-bit Flash ADC

IV. SIMULATION

The performance of this work i.e. 4bit flash ADC was

simulated using Cadence spectre software. The entire flash
ADC circuit is designed in 180nm CMOS technology. The
input to the S/H circuit is a sinusoidal waveform having
amplitude of 1.0Vp-p, operating dc power supply voltage is
±1.8V, and clock frequency is 5GHz. The input signal is Figure 10: Simulated INL
sampled based on the applied clock signal frequency. The
simulated results of the proposed 4-bit flash ADC binary
outputs are shown in figure 9. Here bit B 3 is the most
significant bit and bit B0 is the least significant bit. The
simulated integral non-linearity (INL) error of the proposed
flash ADC is shown in figure 10.The simulated value of
differential non-linearity (DNL) error of the proposed flash
ADC is shown in figure 11. Because INL and DNL are less
than 0.3LSB, this proposed flash ADC has higher linearity.

Fig. 11. Simulated DNL

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 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

REFERENCES

The complete design of the 4-bit flash ADC is completed

using 180nm CMOS technology and the simulated results are
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(SNDR) of 54dB. These attractive specifications of the
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applications such as in high speed wideband wireless receiver
where speed is of utmost importance.

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