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Ee121 HDL Assignment

The document provides a detailed explanation of Verilog design source code and testbench code, including their syntax and components. It outlines the purpose of each component in both the design and testbench, emphasizing their roles in modeling and testing digital circuits. Additionally, it includes tasks for writing Verilog code for various logic gates, adders, subtractors, and multiplexers.

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6 views24 pages

Ee121 HDL Assignment

The document provides a detailed explanation of Verilog design source code and testbench code, including their syntax and components. It outlines the purpose of each component in both the design and testbench, emphasizing their roles in modeling and testing digital circuits. Additionally, it includes tasks for writing Verilog code for various logic gates, adders, subtractors, and multiplexers.

Uploaded by

sonudon161007
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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NAME-YUVANSHU DADHICH

ROLL NO.-CS24B1066

ASSIGNMENT 1

1. Write the complete syntax of a Verilog design


source code and testbench code. Clearly explain
the structure and purpose of each component in
the code.
Ans-

SYNTAX OF DESIGEN SOURCE


CODE
Module
module_name(list_of_ports);
Input/output declarations;
Local net declarations;
Parallel statements;
endmodule
SYNTAX OF TEST BENCH CODE
`timescale <time_unit> / <time_precision>

module <testbench_name>;

reg <input1>, <input2>, ...;

wire <output1>, <output2>, ...;

<module_name> uut (

.<input_port>(<input_signal>),

.<output_port>(<output_signal>)

);

initial begin

// Print output format

$display("Time | Inputs | Outputs");

$monitor("%4t | %b %b | %b", $time, <input1>,


<input2>, <output1>);

<input1> = 0; <input2> = 0; #10;

<input1> = 0; <input2> = 1; #10;

<input1> = 1; <input2> = 0; #10;

<input1> = 1; <input2> = 1; #10;

$finish;

end

endmodule

Verilog Design Source Code and Testbench Code: Structure & Purpose

Verilog is a hardware description language (HDL) used to model electronic systems. It consists
of two main components:
1. Design Source Code – Describes the behavior or structure of the digital circuit.
2. Testbench Code – Tests and verifies the design module using stimulus.

1.Verilog Design Source Code

A Verilog design module consists of the following key components:

Component Purpose
module <name> Defines the module and its name.
Port List Declares input and output signals
Data Types (wire, reg) Specifies internal signal types.
Logic Implementation Defines the circuit behavior using assign (for combinational logic) or
always (for sequential logic)
endmodule Marks the end of the module
Explanation of Components

1. Module and_gate – Declares the module name (and_gate).


2. Input wire A, B – Defines input signals.
3. Output wire Y – Defines output signal.
4. Assign Y = A & B; – Implements the AND logic.
5. Endmodule – Ends the module definition.

2.Verilog Testbench Code

A testbench applies test cases to the design module and observes the output.

Component Purpose
module <testbench_name> Defines the testbench module (has no ports)
Register Declaration (reg) Holds test input values.
Wire Declaration (wire) Captures the design module’s output
DUT Instantiation Connects testbench signals to the design module
initial block Defines test cases and applies stimulus
$monitor and $display Prints output values for debugging.
Simulation Control ($finish) Stops the simulation.
Explanation of Components

1. module and_gate_tb – Declares the testbench module.


2. Registers (reg A, B;) – Stores test values.
3. Wires (wire Y;) – Captures output.
4. DUT Instantiation (and_gate uut (...)) – Connects the testbench to
the design module.
5. initial begin ... end:

 $display – Prints the test header.


 $monitor – Continuously displays signal values.
 #10 – Introduces delays between test cases.
 $finish – Ends simulation.

2. Write a Verilog code that demonstrates at least


seven number representations and seven
different operators in Verilog. Use the display
function to print the results of all operations.

Sol: Behavioral code


Gatelevel

Dataflow

3. Write the design and testbench code for all seven


basic logic gates: AND, OR, NOT, NAND, NOR,
XOR and XNOR. Simulate the code and include
screenshots of the output.

Ans- AND GATE: Testbench code

Design Code
Gatelevel

Dataflow

Behavioral
Output

OR GATE: Testbench Code

Design code
Dataflow
Gatelevel

Behavioral

Output

NOT GATE: Testbench Code


Design Code
Dataflow

Gatelevel

Behavioral

Output
NAND GATE: Testbench Code

Design Code
Dataflow

Gatelevel
Behavioral

Output

NOR GATE: Testbench Code

Design Code
Dataflow
Gatelevel

Behavioral

Output

XOR GATE: Testbench Code


Design Code
Data Flow

Gatelevel

Behavioral

Output
XNOR GATE: Testbench Code

Design Code
Dataflow

Gatelevel
Behavioral

Output

4.Write the design and testbench code for:


Ans: Half Adder
Testbench Code:
Design Code
Dataflow

Gatelevel
Behavioral

Output

FULL ADDER
Testbench Code:
Design Code:
Datatype

Gatelevel

Behavorial

Output
HALF SUBTRACTOR
Testbench Code

Design Code
Dataflow

Gatelevel

Behavorial
Output

FULL SUBTRACTOR
Testbench Code
Design Code
Dataflow

Gatelevel

Behavorial

Output
5.Write the design and testbench code for:
Ans: 2x1 Multiplexer
Testbench Code

Design Code
Dataflow

Gatelevel
Behavorial

Output

4x1 Multiplexer
Testbench Code

Design Code
Dataflow

Gatelevel

Behavorial

Output

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