RAJALAKSHMI ENGINEERING COLLEGE

(AUTONOMOUS)
THANDALAM, CHENNAI 602 105
Department of Electronics and Communication Engineering

DIGITAL LOGIC AND MICROPROCESSOR

EC23232

LAB MANUAL

NAME………………………………………………………………………

BRANCH…………………………………………………………………...

REGISTER NUMBER………………………………………………….....

SEMESTER………………………………………………………………..

ACADEMIC YEAR……………………………………………………….
 TABLE OF CONTENTS

S.NO EXPERIMENT SIGNATURE

DIGITAL LOGIC

1 Design and Implementation of adder, subtractor using logic gates.

Design and Implementation of Binary to Gray and Gray to Binary

2
code converter.
Design and Implementation of Multiplexer and De-multiplexer using logic
3
gates

Design and Implementation of 4-bit Synchronous counters.

4
Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip-
5
Flop
8085 EXPERIMENTS

6 8-bit Arithmetic, Logical and Decimal Arithmetic Operations using 8085.

7 Searching an array of numbers using 8085.

8051 EXPERIMENTS

8 8-bit Arithmetic, Logical operations using 8051

INTERFACING EXPERIMENTS

9 8255 - Parallel interface with 8085

10 8253– Timer interface with 8085

11 Stepper Motor Control using 8051

PIN DIAGRAM of IC`s:
 DESIGN AND IMPLEMENTATION OF ADDER, SUBTRACTOR USING

LOGIC GATES

EXP NO:​ DATE:

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth tables using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 2 input AND gate IC 7408 1
2. 2 input X-OR gate IC 7486 1
3. NOT gate IC 7404 1
4. 2 input OR gate IC 7432 1
3. IC Trainer kit - 1
4. Patch Cords - As required

THEORY

HALF ADDER:

A half adder is a combinational circuit needs two binary inputs and two binary outputs.
The input variables designate the augend and addend bits, the output variables produce the
sum and carry. The half-adder can be implemented with an exclusive –OR and an AND
gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time. In full adder
sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.
HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
FULL SUBTRACTOR:
It is a combination of 2 half subtractors. The first half subtractor is given inputs A and B
and the difference of this along with C is the input to the second half subtractor. Borrows
 of HS are ORed to obtain the borrow of the Full Subtractor

PROCEDURE:

(i)​ Connections are given as per circuit diagram.

(ii)​Switch ON the digital lab trainer kit
(iii)​Inputs are given using the toggle switch
(iv)​Observe the output and verify the truth table.

HALF ADDER

TRUTH TABLE:

Inputs Outputs

A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM:​ K-Map for CARRY:

SUM = A’B + AB’​ ​ ​ ​ CARRY = AB

LOGIC DIAGRAM:
 FULL ADDER- FULL ADDER USING TWO HALF ADDER:

TRUTH TABLE:

Inputs Outputs
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:​ K-Map for CARRY:

SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC

= C(A’B’+AB) + C’(A’B+AB’)
​​ =

LOGIC DIAGRAM:
HALF SUBTRACTOR

TRUTH TABLE:

INPUT OUTPUT
A B Borrow Difference
0 0 0 1
0 1 1 0
1 0 0 0
1 1 0 1

K-Map for DIFFERENCE:​ K-Map for BORROW:

Difference = A’B + AB’​ Borrow = A’B

LOGIC DIAGRAM:

FULL SUBTRACTOR

TRUTH TABLE:
 Inputs Outputs
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:​ K-Map for Borrow:

​ Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C

= A’ (B’C+BC’) +A (B’C’+BC)

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

RESULT: The design of half adder, full adder, half subtractor and full subtractor circuits are
implemented and verified the truth table using logic gates.
 DESIGN AND IMPLEMENTATION OF BIARY TO GRAY AND GRAY TO

BINARY CODE CONVERTORS

EXP NO:​ DATE:

AIM:
To design and construct Binary to Gray and Gray to Binary Code convertor using
logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

2. 2 input X-OR gate IC 7486 1
3. IC Trainer kit - 1
4. Patch Cords - As required

THEORY:

Gray Code, also known as reflected binary code or unit distance code, is a binary
numeral system where two successive values differ by only one bit. Unlike
traditional binary representations, where adjacent numbers can have multiple bits
different, Gray Code ensures that only one bit changes as you move from one value
to the next.
This property makes it particularly useful in various applications where minimizing
errors during transitions is essential.
Gray Code’s primary importance lies in its property of minimizing errors during
binary transitions. In standard binary encoding, multiple bits can change between
consecutive values, potentially leading to errors due to bit propagation delays or
signal glitches.
It minimizes these errors by ensuring that only one bit changes at a time, reducing
the chances of misinterpretation during transitions. This feature is crucial in
applications where accuracy and reliability are paramount.
Application:
●​ Rotary Encoders
●​ Digital Communication
●​ BCD Encoding
●​ Error Detection and Correction

TRUTH TABLE: Binary to Gray Conversion

 K-map to obtain Boolean expressions for the output

​
 Logic Diagram

TRUTH TABLE: Gray to Binary Conversion

K-map to obtain Boolean expressions for the output
Expression for B1

Expression for B0:

LOGIC DIAGRAM:

RESULT:
The design of binary to gray and gray to binary code convertor is implemented successfully
using IC7486.
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DE-MULTIPLEXER
USING LOGIC GATES

EXP NO:​ DATE:

AIM:

To design and implement multiplexer and demultiplexer using logic gates

REQUIREMENTS:

Sl.No. COMPONENT SPECIFICATION QTY.

1 3 Input AND GATE IC 7411 2

2 OR GATE IC 7432 1

3 NOT GATE IC 7404 1

4 IC TRAINER KIT - 1

5 PATCH CORDS - 32

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a

smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and directs it
to a single output line. The selection of a particular input line is controlled by a set
of selection lines. Normally there are 2n input line and n selection lines whose bit
combination determine which input is selected.

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It

takes information from one line and distributes it to a given number of output
lines. For this reason, the demultiplexer is also known as a data distributor.
Decoder can also be used as demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND
gates. The data select lines enable only one gate at a time and the data on the data
input line will pass through the selected gate to the associated data output line.

D0= X S1’ S0’

D1= X S1’ S0

D2= X S1 S0’

D3= X S1 S0

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y =OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3
LOGIC DIAGRAM MULTIPLEXER:

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

 PROCEDURE:

(i)​ Connections are given as per logic diagram.

(ii)​ Logical inputs are given as per logic diagram.
(iii)​ Observe the output and verify the truth table.

RESULT:
The Multiplexer and Demultiplexer were implemented and verified using logic gates
 DESIGN AND IMPLEMENTATION OF 4 BIT SYNCHRONOUS

COUNTER

EXP NO:​ DATE:

AIM:
To design and verify 4 Bit Synchronous Counter.
REQUIREMENTS:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK flip flop IC 7476 2
2. NAND gate IC 7400 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. IC trainer kit - 1
6. Patch cords - As required

THEORY:

K-maps to obtain expressions for J0K0, J1K1, J2K2 and J3K3

​

​
​
LOGIC DIAGRAM: (Up Counter)

TRUTH TABLE:

CLK Q1 Q2 Q3 Q4
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

RESULT: Thus, the design of BCD Counter is designed and truth table verified.
IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT REGISTERS
USING FLIP-FLOP

EXP NO:​ DATE:

AIM:

To design and implement Serial in serial out, Serial in parallel out, Parallel in serial out and
Parallel
in parallel out shift registers using flip-flops

REQUIREMENTS:

SL.NO. COMPONENT SPECIFICATION QTY.

1 D FLIP FLOP IC 7474 2

2 OR GATE IC 7432 1

3 IC TRAINER KIT - 1

4 PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

PIN DIAGRAM:
LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1
SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPU
T
CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0
PROCEDURE:

(i)​ Connections are given as per circuit diagram.

(ii)​Logical inputs are given as per circuit diagram.
(iii)​Observe the output and verify the truth table.

Result:
The shift registers were implemented and verified using flip-flops.
Kit Procedure:

KIT 8051 8085

Address 4000 - 5000 4000 - 5000

Reset - A (enter)
starting SU
Start address (enter) starting address (enter)

SD / SP SU
input address input address
Input (enter) (enter)

GO Press ‘G' Starting address

Execution Starting address (enter) (enter)

SD / SP SU
Output output address (enter) output address (enter)

U (enter) U (enter)
View starting address (enter) starting address (enter)
 8-BIT ARITHMETIC, LOGICAL AND DECIMAL ARITHMETIC
OPERATIONS USING 8085

EXP NO:​ DATE:

AIM:

To write and execute an Assembly Language Program to perform

arithmetic, logical and decimal arithmetic operations using 8085.

ALGORITHM:

1.​ Initialize memory pointer to data location.

2.​ Get the first number from memory and store in accumulator.

3.​ Get the second number in memory and add it to the accumulator.

4.​ Store the results in separate memory locations.

 PROGRAM:

8 BIT ADDITION

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

MVI C,00

LDA

MOV B,A

LDA

ADD B

JNC LOOP

INR C

LOOP STA

MOV A,C

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

8 BIT SUBTRACTION

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

MVI C,00

LDA

MOV B,A

LDA

SUB B

JNC LOOP

INR C

CMA

ADI 01

LOOP STA

MOV A,C

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

8 BIT MULTIPLICATION:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

LDA

MOV B,A

LDA

MOV C,A

MVI A,00

MVI D,00

L2 ADD B

JNC L1

INR D

L1 DCR C

JNZ L2

STA

MOV A,D

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

8 BIT DIVISION:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

MVI C,00

LDA

MOV B,A

LDA

L2 CMP B

JC L1

SUB B

INR C

JMP L2

L1 STA

MOV A,C

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

 8 BIT DECIMAL ARITHMETIC:-

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

MVI C,00

LDA

MOV B,A

LDA

ADD B

DAA

JNC LOOP

INR C

LOOP STA

MOV A,C

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

 AND:

ADDRESS OPCODE MNEMONICS OPERAND COMMENT

MVI A,
MVI B,
ANA B
STA
HLT

OR:

ADDRESS OPCODE MNEMONICS OPERAND COMMENT

MVI A,
MVI B,
ORA B
STA
HLT

EXOR:

ADDRESS OPCODE MNEMONICS OPERAND COMMENT

MVI A,
MVI B,
XRA B
STA
HLT

NOT:

ADDRESS OPCODE MNEMONICS OPERAND COMMENT

MVI A,
CMA
STA
HLT

OBSERVATION:

OPERATION ADDRESS DATA

AND
OR
EXOR
NOT

RESULT:
Thus, an Assembly Language Program to perform arithmetic operations
using 8085 is written and executed successfully.
 SEARCHING AN
ARRAY OF NUMBERS
USING 8085
AIM:
EXP NO:
​ DATE:

To write and execute an Assembly Language Program to search an array of numbers

using8085.

ALGORITHM:

LARGEST/SMALLEST ELEMENT IN AN ARRAY:

1.​ Place all the elements of an array in the consecutive memory locations.
2.​ Fetch the first element from the memory location and load it in the accumulator.
3.​ Initialize a counter (register) with the total number of elements in an array.
4.​ Decrement the counter by 1.
5.​ Increment the memory pointer to point to the next element.
6.​ Compare the accumulator content with the memory content (next element).
7.​ If​ the​ accumulator​ content​ is​ smaller,​ then​ move​
the​memory content(largest/smallest element) to the
accumulator. Else continue.
8.​ Decrement the counter by 1.
9.​ Repeat steps 5 to 8 until the counter reaches zero
10.​Store the result (accumulator content) in the specified memory location.
LARGEST:

ADDRESS OPCODE LABE MNEMONIC OPERAND

L S
LXI H,

MVI B,03

MOV A,M

L2 INX H

CMP M

JNC L1

MOV A,M

L1 DCR B

JNZ L2

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

SMALLEST:

ADDRESS OPCODE LABEL MNEMONICS OPERAND

LXI H,

MVI B,03

MOV A,M

L2 INX H

CMP M

JC L1

MOV A,M

L1 DCR B

JNZ L2

STA

HLT

OBSERVATION:

INPUT OUTPUT

ADDRESS DATA ADDRESS DATA

RESULT:

Thus, an assembly language program to search an array of numbers using 8085

was written and executed successfully.
 8-BIT ARITHMETIC, LOGICAL OPERATIONS USING 8051
EXP NO:​ DATE:

AIM:

To write a program to perform arithmetic and logical operations using 8051.

ALGORITHM:
1.​ Load DPTR with input address.
2.​ Load first data to accumulator
3.​ Increment DPTR
4.​ Load second data to another register.
5.​ Perform arithmetic and logical operation.
6.​ Store the result to a memory location
PROGRAMS:

ADDITION SUBTRACTION

Address Label Mnemonics Operand Address Label Mnemonics Operand

MOV R0,#00 MOV R0,#00

MOV DPTR, MOV DPTR,

MOVX A, @DPTR MOVX A, @DPTR

INC DPTR INC DPTR

MOV B, A MOV B, A

MOVX A, @DPTR MOVX A, @DPTR

ADD A, B SUBB A, B

JNC L1 JNC L1

INC R0 INC R0

L1 INC DPTR INC DPTR

MOVX @DPTR, A MOVX @DPTR, A

INC DPTR INC DPTR

MOV A,R0 MOV A,R0

MOVX @DPTR,A MOVX @DPTR,A

LOOP SJMP LOOP LOOP SJMP LOOP

OBSERVATION:

ADDITION
ADDRESS DATA
INPUT 1
INPUT
INPUT 2
SUM
OUTPUT
CARRY

SUBTRACTION
ADDRESS DATA
INPUT 1
INPUT
INPUT 2
DIFFERENCE
OUTPUT
BORROW

MULTIPLICATION
ADDRESS DATA
INPUT 1
INPUT
INPUT 2
PRODUCT(LSB)
OUTPUT
PRODUCT(MSB)

DIVISION
ADDRESS DATA
INPUT 1
INPUT
INPUT 2
QUOTIENT
OUTPUT
REMAINDER
 MULTIPLICATION DIVISION

Address Label Mnemonics Operand Address Label Mnemonics Operand

MOV DPTR, MOV DPTR,

MOVX A,@DPTR MOVX A,@DPTR

INC DPTR INC DPTR

MOV B,A MOV B,A

MOVX A,@DPTR MOVX A,@DPTR

MUL AB DIV AB

INC DPTR INC DPTR

MOVX @DPTR,A MOVX @DPTR,A

INC DPTR INC DPTR

MOV A,B MOV A,B

MOVX @DPTR,A MOVX @DPTR,A

LOOP SJMP LOOP LOOP SJMP LOOP

AND OR

Address Label Mnemonics Operand Address Label Mnemonics Operand

MOV A,# MOV A,#

MOV B, MOV B,

ANL A, B ORL A, B

MOV DPTR, MOV DPTR,

MOVX @DPTR, A MOVX @DPTR, A

LOOP SJMP LOOP LOOP SJMP LOOP

 XOR NOT

Address Label Mnemonics Operand Address Label Mnemonics Operand

MOV A,# MOV A,#

MOV B, CPL A

XRL A, B MOV DPTR,

MOV DPTR, MOVX @DPTR, A

MOVX @DPTR, A LOOP SJMP LOOP

LOOP SJMP LOOP

OBSERVATION:

OR AND

ADDRESS DATA ADDRESS DATA

OUTPUT OUTPUT

XOR NOT

OUTPUT OUTPUT

RESULT:

Thus an ALP to perform arithmetic and logical operations using 8051 was
written and executed successfully.
 8255 - PARALLEL INTERFACE
EXP NO:​ DATE:

AIM:

To write an assembly language program to interface Programmable peripheral

Interface 8255 in I/O mode and BSR Mode using 8085.
SELECTION WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7​ -​ 1 = I/O MODE, 0 = BIT SET/RESET MODE D6 & D5-00 = MODE 0,
01 = MODE 1, 1X = MODE 2
D4​ -​ 1 = PORT A INPUT, 0= PORT A OUTPUT

D3​ -​ 1 = PORT C (UPPER) INPUT, 0 = PORT C (UPPER) OUTPUT

D2​ -​ 0 = MODE 0, 1 = MODE 1
D1​ -​ 1 = PORT B INPUT, 0= PORT B OUTPUT

D0​ -​ 1 = PORT C (LOWER) INPUT, 0 = PORT C (LOWER) OUTPUT

BIT SET / RESET MODE

D7 D6 D5 D4 D3 D2 D1 D0
D7​ -​ NOT TO BE USED

D4, D5 & D6​ -​ 0 = BIT SET/RESET MODE ACTIVE

D1, D2 & D3​ - 000 – BIT 0
- 001 – BIT 1
- 010 – BIT 2
- 011 – BIT 3
- 100 – BIT 4
- 101 – BIT 5
- 110 – BIT 6
- 111 – BIT 7
D0​ -​ 1 = SET, 0 = RESET

PORT ADDRESS

REGISTER ADDRESS
Control C6
Port A C0
Port B C2
Port C C4
ALGORITHM:

1.​ Initialize the D7 bit for I/O mode and BSR mode.
2.​ Transmit an array of data from input port to output port for I/O mode.
3.​ Set/ Reset a particular bit of an output port for BSR mode.

PROGRAM:

IO MODE
ADDRESS OPCODE MNEMONIC OPERAND COMMENTS
S
4100 MVI A,90
4102 OUT 0C6
4104 IN 0C0
4106 STA 4500
4109 HLT

BSR MODE:

ADDRESS OPCODE MNEMONIC OPERAND COMMENTS

S
4100 MVI A,80
4102 OUT 0C6
4104 MVI A,01
4106 OUT 0C4
4108 MVI A,07
410A OUT 0C6
410C HLT

RESULT:

Thus, the Programmable Peripheral Interface (8255) is programmed in I/O mode using 8085.
 8253 - TIMER INTERFACE
EXP NO:​ DATE:

AIM:-
To write and execute an assembly language program to generate a square wave using
8253.

CONTROL WORD FORMAT:

ALGORITHM:

1.​ Initialize the control word of 8253 to square wave mode.

2.​ Load the MSB and LSB for the square wave.
 3.​ Repeat step 2 to get continuous square wave.

PROGRAM: SQUARE WAVE GENERATOR MODE

ADDRESS OPCODE MNEMONIC OPERAND COMMENTS

S
4100 MVI A,36
4102 OUT 0CE
4104 MVI A,0A
4106 OUT 0C8
4108 MVI A,00
410A OUT 0C8
410C HLT

Amplitude, Time, Frequency,

A(v) T(s) F(Hz)

Calculation of Frequency:

RESULT:
Thus a square wave using 8253 is generated and executed successfully.
 STEPPER MOTOR CONTROL
EXP NO:​ DATE:

To write and execute an ALP to rotate a stepper motor in counter clockwise direction.

ALGORITHM:

1.​ Initialize 8255

2.​ Load the data to accumulator

3.​ Drive the stepper motor circuitry and introduce a delay

4.​ Repeat step 2 & 3 for different data

Table 1 2-Phase switching scheme

Clockwise Anti-clock wise

Step A1 A2 B1 B2 Step A1 A2 B1 B2
1 1 0 0 1 1 1 0 1 0
2 0 1 0 1 2 0 1 1 0
3 0 1 1 0 3 0 1 0 1
4 1 0 1 0 4 1 0 0 1
 PROGRAM:

Address Label Mnemonics Operand Comments

START MOV DPTR, #4500

MOV R0,#04

L1 MOVX A,@DPTR

PUSH DPH

PUSH DPL

MOV DPTR,#FFC0

MOV R2,#04

MOV R1,#0F

L2 MOV R3,#0F

L3 DJNZ R3,L3

DJNZ R1,L2

DJNZ R2,L2

MOVX @DPTR,A

POP DPL

POP DPH

INC DPTR

DJNZ R0,L1

SJMP START

RESULT:

Thus, an ALP to rotate a stepper motor in counter clockwise direction was written and
executed successfully.