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17 Code Optimization 05-02-2025

The document outlines the curriculum for an Embedded Systems course, detailing modules on programming tools, I/O interfacing, real-time operating systems, and applications. It emphasizes code optimization techniques, the use of logic analyzers for debugging, and the programming environment essential for embedded systems development. Additionally, it provides references for textbooks and evaluation methods for students.

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0% found this document useful (0 votes)
6 views52 pages

17 Code Optimization 05-02-2025

The document outlines the curriculum for an Embedded Systems course, detailing modules on programming tools, I/O interfacing, real-time operating systems, and applications. It emphasizes code optimization techniques, the use of logic analyzers for debugging, and the programming environment essential for embedded systems development. Additionally, it provides references for textbooks and evaluation methods for students.

Uploaded by

lanoxof509
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EMBEDDED SYSTEMS

BCSE-305L
Module 4.2:
Programming Tools- Code optimization,
Logical analyzers, Programming
Environment
Dr . A.Sivaranjani
Faculty Id: 21842
School of Computer Science and
Engineering
VIT, Vellore-632014
Tamil Nadu, India
Sivaranjani.A, AP/SCOPE VIT
Module:1 Introduction 5 hours
Overview of Embedded Systems, Design challenges, Embedded processor technology,
Hardware Design, Micro-controller architecture -8051, PIC, and ARM.

Module:2 I/O Interfacing Techniques 8 hours


Memory interfacing, A/D, D/A, Timers, Watch-dog timer, Counters, Encoder & Decoder,
UART, Sensors and actuators interfacing.

Module:3 Architecture of Special Purpose Computing System 6 hours


ATM, Handheld devices, Data Compressor, Image Capturing Devices–Architecture and
Requirements, Challenges & Constraints of special purpose computing system.

Sivaranjani.A, AP/SCOPE VIT


Module:4 Programming Tools 7 hours
Evolution of embedded programming tools, Modelling programs, Code optimization, Logic
analyzers, Programming environment.

Module:5 Real Time Operating System 8 hours


Classification of Real time system, Issues & challenges in RTS, Real time scheduling schemes-
EDF-RMS & Hybrid techniques, eCOS, POSIX, Protothreads.

Module:6 Embedded Networking Protocols 5 hours


Inter Integrated Circuits (I2C), Controller Area Network, Embedded Ethernet Controller, RS232,
Bluetooth, Zigbee, Wifi.

Module:7 Applications of Embedded Systems 4 hours


Introduction to embedded system applications using case studies – Role in Agriculture sector,
Automotive electronics, Consumer Electronics, Industrial controls, Medical Electronics.

Module:8 Contemporary Issues


Sivaranjani.A, AP/SCOPE VIT
Text Book
1. Marilyn Wolf, Computers as Components – Principles of Embedded Computing System Design,
Fourth Edition, Morgan Kaufman Publishers, 2016.

Reference Books
1. Embedded Systems Architecture, Programming and Design, by Raj Kamal, McGraw Hill
Education, 3e, 2015.
2. Embedded System Design A Unified Hardware/Sofware Introduction, by Vahid G Frank and
Givargis Tony, John Wiley & Sons, 2009.

Mode of Evaluation: CAT, written assignment, Quiz, FAT.


Recommended by Board of Studies 04-03-2022 Approved by Academic Council No. 65 Date
17-03-2022

Sivaranjani.A, AP/SCOPE VIT


CODE OPTIMIZATION
Code Optimization in Embedded Systems is the process of improving software
to run efficiently on hardware with limited resources (CPU, memory, power). It
ensures that the code executes faster, uses less memory, consumes less power, and
meets real-time constraints.
Why is Code Optimization Important in Embedded Systems?
✅ Reduces execution time (important for real-time processing).
✅ Minimizes memory usage (saves RAM & flash storage).
✅ Lowers power consumption (critical for battery-operated devices).
✅ Enhances reliability (prevents crashes due to memory overflow).
✅ Ensures real-time performance (meets deadlines in critical applications like automotive,
medical devices, etc.).

Sivaranjani.A, AP/SCOPE VIT


Code optimization techniques at different levels:
3⃣ Memory Optimization
1⃣ Compiler-Level Optimization ❖ Use smaller data types (uint8_t (1 byte -8 bits))
❖ Dead code elimination (removes unused instead of int- (4 bytes (32 bits)).
code). ❖ Avoid dynamic memory allocation (malloc).
❖ Loop unrolling (reduces loop overhead). ❖ Pack structures to save memory
❖ Inlining functions (removes function call (__attribute__((packed))).
overhead). 4⃣ Hardware Optimization
2⃣ Code-Level Optimization ❖ Use Direct Register Access instead of slow
❖ Use bitwise operations instead of arithmetic. library functions.
❖ Minimize function calls (use inline functions). ❖ Utilize DMA (Direct Memory Access) to offload
❖ Reduce redundant calculations inside loops. CPU.
❖ Optimize Interrupt Service Routines (ISRs) to
be short and efficient.

Sivaranjani.A, AP/SCOPE VIT


Type of Code optimization techniques:
1⃣ Machine-Independent Optimization
❖ These optimizations improve the efficiency of code without considering the hardware or
system architecture.
❖ They are performed at the compiler level and apply to any machine or processor.

2⃣ Machine-Dependent Optimization
❖ These optimizations take advantage of specific hardware architecture to improve
performance.
❖ They depend on the processor, memory hierarchy, registers, and instruction set.

Sivaranjani.A, AP/SCOPE VIT


Flow of Compilation Process & Error Handling
A compiler converts a high-level source program (e.g., C, Python) into a target
program (machine code). This process includes front-end processing, optimization,
and code generation.

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Loop Optimization
Loop optimization is crucial for
improving execution speed,
reducing CPU load, and optimizing
memory usage in embedded
systems and high-performance
applications.
Sivaranjani.A, AP/SCOPE VIT
Sivaranjani.A, AP/SCOPE VIT
Code Motion:

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t=4;
i=1; while(t<40)
while(i<10) {
{ y=t;
y=i*4; t=t+4;
i=i+1; }
}

Sivaranjani.A, AP/SCOPE VIT


Sivaranjani.A, AP/SCOPE VIT
Duplicates the body of the loop multiple times, in order
to decrease the number of times the loop condition is
tested.
for(i=0;i<100; i++) for(i=0;i<50; i++)
{ {
display( ); display( );
} display();
}

Sivaranjani.A, AP/SCOPE VIT


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Sivaranjani.A, AP/SCOPE VIT
Dead Code Elimination
Dead code is code that can never be executed. Dead code can be
generated by programmers, either inadvertently or
purposefully. Dead code can also be generated by compilers.

Dead code can be identified by reachability analysis, finding the


other statements or instructions from which it can be reached.

If a given piece of code cannot be reached, or it can be reached


only by a piece of code that is unreachable from the main
program, then it can be eliminated.

Sivaranjani.A, AP/SCOPE VIT


Register Allocation
Register allocation is a very important compilation phase. Given a block of
code, we want to choose assignments of variables (both declared and
temporary) to registers to minimize the total number of required registers.

Sivaranjani.A, AP/SCOPE VIT


Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Register Allocation

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Cache-oriented loop optimizations

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Cache-oriented loop optimizations

Sivaranjani.A, AP/SCOPE VIT


Cache-oriented loop optimizations

Sivaranjani.A, AP/SCOPE VIT


Cache-oriented loop optimizations
● Once the a[0][1] access brings that line into the cache, it remains there for the a[0][2] and
a[0][3] accesses because the b[] accesses are now on the next line.
● However, the scenario repeats itself at a[1][0] and every four iterations of the cache.
● One way to eliminate the cache conflicts is to move one of the arrays.
● We do not have to move it far.
● If we move b’s start to 4100, we eliminate the cache conflicts. However, that fix will not
work in more complex situations.
● Moving one array may only introduce cache conflicts with another array. In such cases, we
can use another technique called padding.
● If we extend each of the rows of the arrays to have four elements rather than three, with
the padding word placed at the beginning of the row, we eliminate the cache conflicts. In
this case, b[0][0] is located at 4100 by the padding.
● Although padding wastes memory, it substantially improves memory performance.
● In complex situations with multiple arrays and sophisticated access patterns, we have to
use a combination of techniques, relocating arrays and padding them to be able to
minimize cache conflicts.

Sivaranjani.A, AP/SCOPE VIT


Sivaranjani.A, AP/SCOPE VIT
Logic analyzer
A logic analyzer is an electronic measuring device that
records and displays the time course of several digital
signals.

Logic Analyzer is an excellent tool for checking and


debugging digital circuits such as embedded systems,
electronic control units, computer peripherals, etc.

Logic analyzers have significantly more inputs (typically 16 to


several hundred) than oscilloscopes but display only discrete
logic values on the Y-axis.

These include the Boolean truth values of binary digital false


("0") and true ("1"). Sivaranjani.A, AP/SCOPE VIT
A logic analyzer can convert the acquired data into timing
logic analogic analyzer
diagrams, protocol decodings, state machines, and assembly
language. lyzer

Some logic analyzers can detect glitches and set up and hold
time violations to troubleshoot elusive, intermittent problems.

During software/hardware integration, logic analyzers track


the embedded software's execution and analyze the program
execution's efficiency.

Some logic analyzers correlate source code with specific


hardware activity in your design.
Sivaranjani.A, AP/SCOPE VIT
logic analogic analyzer
Logic Analyzer vs. Oscilloscope
● Logic Analyzer: lyzer
○ Used for analyzing multiple digital signals (16 to several hundred
inputs).
○ Displays only logic values (0 and 1).
○ Converts data into timing diagrams, protocol decodings, and state
machines.
● Oscilloscope:
○ Used for viewing analog waveforms.
○ Measures voltage changes over time.
○ Displays waveforms in continuous form.

Sivaranjani.A, AP/SCOPE VIT


Time view
Visualizes signal
transitions over
time.

Useful for timing


analysis, such as
measuring pulse
width, frequency,
and signal delays.

Sivaranjani.A, AP/SCOPE VIT


State Machine view
Represents state
transitions in a discrete
system.

Ideal for analyzing


systems with defined
states, like finite state
machines or control
systems.

Sivaranjani.A, AP/SCOPE VIT


Protocol view
Decodes and presents
protocol data in a
readable format.

Perfect for monitoring


and debugging
communication protocols
like I2C, SPI, UART,
CAN.

Sivaranjani.A, AP/SCOPE VIT


Importance of Logical Analyzer
Troubleshooting microprocessor-based designs requires more
inputs than most conventional analog oscilloscopes can
provide.

A typical logic analyzer has 8 or more channels and is


particularly useful for studying the timing of digital signals
or data on a bus.

For example, an address, data or control bus of a


microprocessor. They can decode the information on
microprocessor buses and display it in a descriptive way.

Sivaranjani.A, AP/SCOPE VIT


Importance of Logical Analyzer
• A logic analyzer measures and analyzes signals differently
than an oscilloscope.
• The logic analyzer does not measure analog data.
• Instead, it recognizes logical thresholds.
• When a logic analyzer is connected to a digital circuit, only
two logic states of the signal are of interest.
• When the input is above the threshold voltage (V), the
level is called a “high” or “1”; conversely, the level below
Vth is a “low” or “0”.
• It will store a “1” “true” or a “0” “false” depending on the
level of the signal relative to the voltage threshold.
Sivaranjani.A, AP/SCOPE VIT
Modular Logical Analyzers
Modular logic analyzers are composed of a chassis or mainframe and logic
analyzer modules.

The housing contains the display and control elements, the computer and
several slots in which the actual measurement hardware is installed.

The modules each have a certain number of channels, of which you can also
connect many modules to achieve a high number of channels.

They are among the more expensive devices and offer the user a high level
of functionality due to the high number of channels.

Sivaranjani.A, AP/SCOPE VIT


Portable Logical Analyzers
Portable logic analyzers (stand-alone logic
analyzers) are more mobile than modular logic
analyzers because they consist of one device
including a screen.

In general, they are less conductive than the modular


logic analyzers. (Standalone Logic Analyzers → Fixed
features, cannot be expanded easily)

Sivaranjani.A, AP/SCOPE VIT


PC- based Logical Analyzers
PC-based logic analyzers are compact and connect
directly to a computer via an Ethernet or USB cable.

This makes them cheaper because they use the existing


keyboard, screen and processing power of the PC.

However, they have lower performance compared to


modular and portable logic analyzers.

Sivaranjani.A, AP/SCOPE VIT


Programming Environment in Embedded Systems
A programming environment refers to the set of tools, software, and hardware used to write,
compile, debug, and deploy programs in an embedded system or general computing system.

● Integrated Development Environments (IDE): Keil, IAR Embedded Workbench, Eclipse,


Arduino IDE.
● Compilers & Toolchains: GCC, ARM GCC, TI Code Composer Studio.
● Programming Languages: C, C++, Assembly, Python (for higher-level applications).
● Real-Time Operating Systems (RTOS): FreeRTOS, CMSIS-RTOS, ThreadX.
● Simulators/Emulators: QEMU, Proteus for hardware/software simulation.
● Debugging Tools: JTAG, SWD, GDB, OpenOCD.
● Version Control: Git, SVN for source code management.
● Build Systems: Makefiles, automated build with dependencies.
● Libraries & Middleware: CMSIS, HAL for easier hardware abstraction.
● Target Hardware: Microcontrollers (e.g., STM32, ESP32), FPGAs, Single-board computers (e.g.,
Raspberry Pi).

Sivaranjani.A, AP/SCOPE VIT

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