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Architecture

The document is an assignment for a Diploma in Computer Studies focusing on computer architecture, covering key concepts such as mnemonic instructions, machine code, registers, and the fetch-decode-execute cycle. It includes definitions, addressing modes, memory hierarchy, and terminologies related to computer systems. Additionally, it discusses the J-K flip-flop circuit design and the generation of a 20-bit address in the 8086/8088 processor.

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Vïncæñt Mübïtå Jr.
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0 views

Architecture

The document is an assignment for a Diploma in Computer Studies focusing on computer architecture, covering key concepts such as mnemonic instructions, machine code, registers, and the fetch-decode-execute cycle. It includes definitions, addressing modes, memory hierarchy, and terminologies related to computer systems. Additionally, it discusses the J-K flip-flop circuit design and the generation of a 20-bit address in the 8086/8088 processor.

Uploaded by

Vïncæñt Mübïtå Jr.
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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MONGU TRADES TRAINING INSTITUTE MANAGEMENT BOARD

IT SECTION

CERTIFICATE IN COMPUTER STUDIES

TERM THREE ASSIGNMENT

PROGRAM: DIPLOMA IN COMPUTER STUDIES

COURSE: ARCHITECTURE

NAME: VINCENT WAMULUME MUBITA

EXAM NO: 831116

LECTURER: MR CHAMBWA
- i) Mnemonic: A symbolic name for a single executable machine language
instruction, used for ease of programming.

- ii) Machine Code Instruction: The lowest-level representation of a compiled


or assembled computer program, understood directly by the CPU.

- iii) Electronic Clock: A timing device that provides a sequence of electronic


pulses used to synchronize operations in a computer.

- iv) Upward Compatibility: The ability of older software to run on newer


hardware or platforms without modification.

- v) Portability of a System: The ease with which software can be transferred


from one system environment to another.

b) Registers:

- i) Data Out Register: Holds data that is to be sent to an output device.

- ii) Interrogate Register: Used to test the status of various conditions or


indicators in the computer.

- iii) Memory Buffer Register (MBR): Temporarily holds data being transferred
to or from memory.

- iv) Instruction Sequence Register: Keeps track of the current instruction


being processed.

- v) Index Register: Used to modify operand addresses during the execution


of a program.

c) Fetch Decode Execute Cycle:

1. Fetch: The CPU reads an instruction from memory.

2. Decode: The control unit translates the fetched instruction into signals.

3. Execute: The CPU carries out the decoded instruction.

4. Store: The result of the execution is stored back in memory or registers if


needed.
d) Bus Types:

- i) MBR(MEMORY BUFER REGISTER) : Data Bus

- ii)MAR(MEMORY ADDRESS REGISTER ): Address Bus

a) Definitions:

- i) Source Code: The original code written by a programmer in a high-level


programming language.

- ii) Object Code: The machine code generated by a compiler or assembler


from source code.

- iii) Instruction Set: The complete set of instructions that a CPU can execute.

- iv) Assembler: A tool that translates assembly language into machine code.

b) Common Structure of a Machine Code Instruction in a 32-bit Machine:

Imagine this layout:

| Opcode (8 bits) | Source Register (8 bits) | Destination Register (8 bits) |


Operand (8 bits) |

This breaks down the instruction into parts that specify the operation, the
source of the data, the destination for the result, and any additional data.

c) Subsets of a Processor Instruction Set:

1. Data Transfer Instructions:MOV R1, R2

2. Arithmetic Instructions: ADD R1, R2, R3

3. Logical Instructions: AND R1, R2, R3

4. Control Instructions: MP 0x1000

5. Input/Output Instructions: IN R1, PORT


6. String Instructions: MOVSB

d) Common Modes of Addressing:

1. Immediate Addressing: The operand is part of the instruction.

2. Direct Addressing: The address of the operand is given in the instruction.

3. Indirect Addressing: The address of the operand is specified by a register.

4. Indexed Addressing: The final address is determined by adding a constant


value to the contents of a register.

a) Nine Levels of Memory Hierarchy (2 marks):

1. Registers

2. L1 Cache

3. L2 Cache

4. L3 Cache

5. Main Memory (RAM)

6. Solid State Drive (SSD)

7. Hard Disk Drive (HDD)

8. Optical Disk

9. Magnetic Tapes

b) Concepts Explained (6 marks):

- i) Direct Memory Access (DMA) I/O: It allows devices to transfer data


directly to or from the memory without involving the CPU, improving speed
and efficiency.

- ii) Content Addressable Memory (CAM): This type of memory is accessed


based on the content stored rather than the address, ideal for applications
like cache memory and databases.

- iii) Modes of Operation of the DMAC:


- Burst Mode: Transfers a block of data in one continuous operation.

- Cycle Stealing Mode: Transfers data one byte or word at a time,


interleaving with CPU cycles.

c) Terminologies Explained (7 marks):

- i) Emulation: Mimicking the functions of one system using a different


system, allowing software or hardware to run as if it were on the original
system.

- ii) Simulation: Creating a virtual model of a system to study its behavior


under different conditions.

- iii) UART (Universal Asynchronous Receiver/Transmitter): A hardware device


that manages asynchronous serial communication, sending and receiving
data bit by bit.

- iv) USART (Universal Synchronous/Asynchronous Receiver/Transmitter):


Similar to UART but can handle both synchronous and asynchronous
communication.

d) Relationship between Propagation Delay and Skew in Parallel Transmission


(1 mark):

Propagation delay is the time it takes for a signal to travel from the source to
the destination. Skew occurs when there is a difference in propagation delays
between different signal paths in a parallel transmission, leading to timing
mismatches.

e) J-K Flip-Flop Circuit Design (4 marks):

Truth Table:

| J | K | Q (next) |

| 0 | 0 | Q (same) |

|0|1|0 |
|1|0|1 |

| 1 | 1 | Q’ (toggle)|

Schematic Diagram:

![J-K Flip-Flop Schematic](URL)

Functionality Explanation:

- Inputs J and Kdetermine the next state of the flip-flop.

- When J=0 and K=0, the flip-flop holds the current state.

- When J=0 and K=1, it resets the output to 0.

- When J=1 and K=0, it sets the output to 1.

- When J=1 and K=1, it toggles the output.

a) Generating 20-bit Address:

The 8086/8088 Processor uses segment registers and offsets to generate a


20-bit address. Each segment register (like CS, DS, SS, or ES) holds a 16-bit
value, which represents the start of a 64 KB segment in memory. The offset,
also a 16-bit value, is added to the segment address (shifted left by 4 bits) to
form the final 20-bit physical address.

So, the 20-bit address is 10414 Hex.

b) Addressing Modes:

- i) Immediate Addressing Mode: The operand is part of the instruction itself.


For example, in MOV AL, 0x, the value 5 is the immediate operand.
- ii) Direct Addressing Mode: The instruction specifies the memory address of
the operand. For example, MOV AL, [1234H] accesses the memory location
1234H directly.

- iii) Indirect Addressing Mode: The address of the operand is specified


indirectly via a register. For example, MOV AL, [BX] means the operand’s
address is stored in the BX register.

c) Registers of the 8086/8088 Processor:

- i) CS (Code Segment): Holds the base address for the current code
segment, used during instruction fetching.

- ii) SS (Stack Segment): Contains the base address for the stack segment,
which is used for stack operations.

- iii) DS (Data Segment): Contains the base address for the data segment,
used to hold variables and other data.

- iv) ES (Extra Segment): An additional segment register, often used for


string operations and other purposes to provide flexibility.

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