International Conference on Communication and Signal Processing, April 6-8, 2017, India

Design of Reconfigurable LFSR for VLSI IC

Testing in ASIC and FPGA
Devika K N and Ramesh Bhakthavatchalu

Abstract—This paper focus on the design of a reconfigurable Logic BIST design includes on-chip/board circuitry to
Linear Feedback Shift Register (LFSR) for Very Large Scale provide test patterns and to analyze output responses. It can
Integration (VLSI) Integrated Circuit (IC) testing. The perform the test internal to the chip so that the need for
advancement in VLSI technology have made chip testing more
complicated which has lead to the popularity of Logic Built In complex external testing equipment is greatly reduced. It not
Self Test(LBIST) compared to Automatic Test Equipment(ATE). only reduces the cost of testing but also allows rapid testing of
Logic BIST allows in-built chip testing with the help of an the circuit [1]. It guarantees complete fault coverage at the
additional hardware structure inside the circuit. The test cost of area occupancy of about 15% overall chip area. In
patterns are not applied by ATE but are generated by inbuilt Logic BIST architecture PRPG act as the test pattern generator
testing circuits. Thus it reduces testing costs considerably. LFSR and MISR acts as the output response analyzer. Test patterns
is commonly used as a test pattern generator since it is more
efficient than binary counters. Reconfigurable LFSR can be used
generated by PRPG are fed as inputs to the circuit under test.
as the test pattern generator inside Logic BIST to improve the The corresponding outputs from MISR is compared with the
fault coverage of IC testing. As per requirement it can be expected outputs (Golden signature) using a comparator to
configured to generate maximum length sequence or any length check whether the circuit is faulty or fault-free [2],[3].
patterns depending on the feedback polynomial provided. It Alternating Variable Run-length (AVR) code scheme is used
increases the random patterns generated that are applied as test for test data reduction in LFSR [4].
vectors. The proposed LFSR architecture is simulated in
Modelsim RTL simulator. The different sized (16, 32, 64) The critical components in Logic BIST comprises of a
programmable LFSR structures is synthesized in Xilinx Spartan Pseudo Random Pattern Generator (PRPG) and Multiple Input
3E for implementing LFSR on FPGA. Four structural
Shift Register (MISR). Pseudo Random Pattern Generator is
representations such as Modular, Standard, Hybrid and
Complete LFSR are implemented. All the designs are synthesized implemented using an LFSR which generates random test
for ASIC in RTL compiler using 90nm standard cell technology patterns that are applied to the circuit to be tested [5],[6].
library. The results of the proposed programmable designs are LFSR structure mainly includes flip-flops, XOR gates and
analyzed for speed, power and area. multiplexers that make it reconfigurable. It is a shift register
whose input bit to LSB flipflop is a linear function of pre-
Index Terms—PRPG, Reconfigurable LFSR, primitive vious states of other flipflops. XOR gates provide the linear
polynomial, FPGA, ASIC
functionality. Many research work have been done to make
LFSR reconfigurable [7]-[8]-[9]. Most common application of
I. INTRODUCTION

T
LFSR is in Logic BIST architectures as test pattern generators
HE ever increasing complexity of IC designs has made the [10]. One of the approaches adds reconfigurability to the
testing of VLSI chips more difficult and cumbersome. Due design by relying on multiplexers [11]. But it adds to circuit
to the advancement in manufacturing technologies it has complexity since the proposed technique demands the
become extremely important and difficult to test the VLSI requirement of n-1 XOR gates for n-bit LFSR even if the
chips for commonly occurring faults such as stuck at faults feedback polynomial demands less number of taps. Another
and bridging faults. This lead to the development of a new paper designs n-bit LFSR over GF(2p) by converting it into
testing technology called Logic Built in Self-Test. equivalent logic over GF (2) but with a higher order size
[13].There are a wide variety of applications of
To ensure safety and durability, infield testing should be
LFSR[12],[14],[15]. It is being used as the key stream
Logic BIST is an inbuilt testing circuitry that tests the
generators in cryptographic field for the past few decades [16].
structural integrity or quality of the chip after manufacturing.
In this paper an n-bit reconfigurable LFSR that generates
sequences of maximum length or less has been designed and
implemented. The proposed design provides flexibility in
terms of both, feedback polynomial and size of LFSR.
Devika K N and Ramesh Bhakthavatchalu are with Department of
Electronics and Communication Engineering, Amrita School of Engineering,
Amritapuri, Amrita Vishwa Vidyapeetham, Amrita University, India.(e-mail:
[email protected], [email protected]).

978-1-5090-3800-8/17/$31.00 ©2017 IEEE

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 The design inserts XOR gates only at required positions absence of tap position.
contributed by the primitive or non-primitive polynomials. For example, in the feedback polynomial
Muliplexers are added to the structure to load the initial values
into the LFSR design. It is simulated and synthesized using

Fig. 2. N-bit Modular LFSR architecture

Fig. 1.Typical LFSR architecture

verilog on the Xilinx Spartan 3E for implementation in FPGA

nd in Encounter RTL compiler for implementation in ASIC
[17]. Reconfigurable LFSR is designed in its different forms
to study and compare their performance to determine the
efficient configuration. Fig. 3. N-bit Standard LFSR architecture

The structure of the paper proceeds as follows: Section II

describes the architecture of LFSR and its different types. Sec- x16 + x14 + x13 + x11 + 1 (2)
tion III discusses how programmable LFSR is implemented. The term, one represents the input to first flip-flop, and
Section IV shows the simulation and synthesis results of 16, powers of x terms represents the tapped bits.
32 and 64 bit LFSR in Xilinx and RTL compiler. Section V Those polynomials that could divide 1 + xT completely but
concludes the paper and discusses future scope in this field. does not divide any other polynomials of the form 1 + x i are
called primitive polynomials, where i<1. The significance of
II. ARCHITECTURE OF LFSR primitive polynomials is that maximum length sequences of T
LFSR is basically a shift register where each clock signal = 2n – 1 can be generated. So these polynomials are fed to
advances the data from one register to another [18]. Here some LFSR in Logic BIST applications.
bits of the shift register are XORed to form a linear feedback Due to the capability to generate random patterns and
to drive the input bit of LFSR. Taps are those selected bits of because of error detection and correction properties LFSR is
the previous states that influence the input bit. A chain of such commonly used to design the main components in LBIST
taps depending on the feedback polynomial is XORed to form architecture.
the feedback loop. Characteristic polynomial of degree n over
. Different types of LFSR includes, i) Standard LFSR ii)
GF (2) defines the internal structure of an n-bit LFSR where
Modular LFSR iii) Complete LFSR iv) Hybrid LFSR
coefficients hi denote the existence of feedback path.
Characteristic polynomial is given by m(x) [18] A. Standard LFSR
m(x) = 1 + h1x + h2x2 + :::::::hn 1xn 1
+ hnxn (1) Standard LFSR also called as Fibonacci LFSR or external
XOR LFSR is a shift register XOR gates representing the tap
LFSR can generate different pseudo random sequences positions of the feedback polynomials are concatenated to
based on the feedback polynomial provided. The arithmetic produce a new output bit. This single bit output is given as
operations in LFSR are done over finite field of polynomial feedback input to the last flipflop in the structure. Fig.3 shows
mod 2. an N-bit Standard LFSR
This finite field is called Galois field denoted as GF (p)
where p is the number of elements in the field. GF (2) is the
B. Modular LFSR
binary field over which all the arithmetic operations are
performed in LFSR. Therefore every addition operation is Modular LFSR called as galois, internal XORs, or one-to-
equivalent to XOR and every multiplication happens as AND many LFSR is another form LFSR generating the same
operation. So the coefficients of the characteristic polynomials patterns as that of conventional one. The only difference lies
have either 0 or 1 as its value that indicates the presence or in the connection of taps in feedback polynomials to the

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flipflops. The XOR gates are connected immediately after the where ^xj indicates that the XOR gate with one input taken
flipflop depending on tap positions. The output of these gates from the jth stage output of the LFSR is connected to the
feedback path and not between stages. Fig. 5 Shows the
architecture of Hybrid LFSR. The advantage of Hybrid
structure of LFSR compared to modular and standard form is
that the number of XOR gates required can be reduced from
‘m’ XOR gates to (m-1)/2 in hybrid form. It makes use of a
feedback structure from jth output stage. A modular structure
is utilized from first to (j-1)th registers. So Hybrid LFSR is
more efficient in terms of area, number of gates and speed.

III. PROPOSED LFSR ARCHITECTURE

Fig. 4. Architecture of Complete LFSR This paper presents the design of a simple reconfigurable
LFSR. Normally LFSR generates 2n – 1 states if the give
polynomial is primitive or less number of states if the entered
polynomial is non-primitive. Programmable LFSR increases
the randomness of the output. This LFSR uses D-flipflops,
XOR gates and multiplexers. Fig. 6.shows the proposed
architecture of LFSR. XOR gates are inserted between the
flipflops depending on the value of chain which represents the
required polynomial in the design. The choice of taps
determines how many values of PN sequence is there before
repetition. That gives the cycle PN sequence. Presence of
Fig. 5. Architecture of Hybrid LFSR multiplexers in the structure makes LFSR reconfigurable. The
select signal decides whether to load the flipflops or to shift
is fed to the immediate next flipflop. The advantage of this the values in the register. Initial value is loaded into the LFSR
structure over the standard form is that the critical path if the select signal is zero. In the other case it does the shifting
contains a maximum of only one XOR gate in between the operation according to the feedback polynomial provided. The
two flipflop compared to other where it includes all XOR length of the LFSR designed is also made programmable to
gates as per the number of taps. So Modular LFSR is faster in have an n-bit LFSR.
terms of execution compared to the Standard one because
In this paper standard, modular, complete as well as hybrid
XOR operations can be implemented a word at a time. Thus LFSR’s are made to be programmable. Complete LFSR uses
software implementation of galois LFSR is efficient. Fig. 2. the same design as that of standard LFSR, except that a
shows an N-bit Modular LFSR. additional circuitry is added. This circuitry consists of a NOR
gate which takes in all the flipflop output as inputs and pass it
to an XOR gate. XOR gate also takes in the value coming
C. Complete LFSR
form the feedback path of standard LFSR.The output of this
All LFSR are designed to generate a maximum length XOR gate is given as feedback in the reconfigurable LFSR.
sequence of upto 2n -1only. Complete form of architecture is By doing so LFSR can generate all 2n exhaustive patterns
shown in fig. 4. The presence of an all-zero sate can move improving the fault coverage. In top-bottom hybrid LFSR
LFSR into a locked-state condition. Modified form of LFSR design number of XOR gates is reduced using both standard
that also include an all zero state is called complete LFSR. and modular configurations in the design.
Complete LFSR can be constructed from standard LFSR by
inserting an XOR gate into the last stage of the LFSR, and a IV. SIMULATION AND SYNTHESIS RESULTS
NOR gate with n-1 inputs is used as a zero-detector. Thus a The proposed design of LFSR is described in verilog HDL,
complete LFSR could generate 2n patterns for a primitive simulated in Modelsim 6.5 RTL simulator and Xilinx ISE is
polynomial feedback LFSR [18]. the software tool used for synthesis in FPGA. Encounter RTL
compiler is the EDA tool used for the synthesis of the design
D. Hybrid LFSR in ASIC.
A polynomial over GF (2) f(x) = 1+ m(x) + q(x), be said to
be fully decomposable if both m(x) and q(x) have no common
terms and there exists an integer j such that q(x) = xjm(x),
where j<1. Then the corresponding polynomial can be
expressed as
f(x) = 1+m(x)+xj m(x) (3)

Then a (hybrid) top–bottom LFSR can be constructed

using the connection polynomial:
Fig. 6. Proposed architecture of LFSR
p(x) = 1+^xj + xj m(x) (4)

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 A. Simulation results
TABLE III
The figure below shows the result after simulation of 16 bit PARAMETRIC ANALYSIS FOR DIFFERENT 64 BIT LFSR IN XILINX SPARTAN 3E
standard LFSR generating 65535 patterns. The clock period FPGA
applied is of 20ns for a seed value of 10. Fig. 7.shows the Performance parameters Standard Modular Complete hybrid
simulation results of a 16-bit LFSR. Number of slices 37 37 45 37
Number of Flipflops 64 64 64 64
Number of 4 input LUTs 65 64 81 65
Number of bonded IOBs 131 131 131 131
B. Synthesis results in Xilinx ISE tool Numbre of GCLKs 1 1 1 1
Max frquency of
The results were analysed after synthesis in Spartan 3E operation(GHz) 368.684 509.671 222.526 378.652
FPGA for 16, 32 and 64 bit LFSR in its various
configurations. On analysis, it has been observed that modular
LFSR has maximum frequency of operation of about 509 implementation. Hybrid LFSR is efficient in terms of number
MHz compared to standard, complete or hybrid structure for of gates used and also had greater speed of execution than
any bit configuration. Complete LFSR has least speed of Standard LFSR. Fig. 9 shows the ASIC synthesis of modular
execution due to more number of gates involved in its critical 16-bit LFSR.
path. Hybrid LFSR has frequency of operation comparable to
that of Standard LFSR. Memory utilization was found to be V. CONCLUSION AND FUTURE SCOPE
same for all LFSR. Fig. 8 shows the synthesis of modular 16- This paper presents a reconfigurable Logic BIST
bit LFSR in Spartan 3E FPGA. Table 1, 2, 3 shows the architecture where every component was designed to be
parametric analysis of 16, 32 and 64-bit LFSR respectively. programmable. This design thus ensures self-testing of any
kind of circuitry with varying configurations. PRPG and
C. Synthesis results in RTL compiler MISR structures were made reconfigurable by adding
In ASIC synthesis of all LFSR designs it was observed that multiplexers into its designs and providing flexibility in the
modular LFSR had maximum speed of execution of about position of tap insertions which determines the feedback
1.37 GHz and less switching power. Table 4 displays the polynomials and the patterns generated. For MISR, XOR gates
synthesis results of different bit LFSR in RTL compiler. Area were added to every flip-flop inputs depending on the number
utilization was more in Complete LFSR due to more number of primary outputs of the CUT. Comparator and ROM were
of gates used for its also designed to compare and store any number of inputs with
varying size.

The analysis of this work shows that modular structure is

efficient in terms of speed of execution and in gate utilization
compared to other forms of Reconfigurable LFSR or MISR.
Fig. 10 shows a comparison of power consumption among all
types of LFSR. Fig. 11 shows the Gate utilization by various
LFSRs in ASIC synthesis. Hybrid form due to its efficient
configurations utilized less number of gates and had speed
comparable to standard one. Complete LFSR/MISR even
Fig. 7. Simulation result of a 16bit standard LFSR with seed value 10 though generated 2n patterns showed more area occupancy.
TABLE I As future scope, the power consumed by the structure can
PARAMETRIC ANALYSIS FOR DIFFERENT 16 BIT LFSR IN XILINX SPARTAN 3E
FPGA be reduced further by including sleep transistors in the design
or by using power gating techniques
Performance parameters Standard Modular Complete hybrid
Number of slices 10 9 14 10 TABLE IV
Number of Flipflops 16 16 16 16 SYNTHESIS RESULTS OF 16, 32 AND 64 BIT LFSR IN RTL COMPILER
Number of 4 input LUTs 17 16 25 17
Number of bonded IOBs 35 35 35 35
Numbre of GCLKs 1 1 1 1 Type of
Max frquency of LFSR Size Area(nm2) Mapped gates Power(nW) Speed(GHz)
operation(GHz) 378.652 509.671 211.759 378.652 Standard 16 155.27 51 8319.64 1.144
Modular 16 155.95 51 8114.89 1.373
TABLE II Complete 16 164.16 57 8687.14 0.789
PARAMETRIC ANALYSIS FOR DIFFERENT 32 BIT LFSR IN XILINX SPARTAN 3E Hybrid 16 152.53 50 8133.43 1.188
FPGA Standard 32 303.01 99 14532.22 1.444
Modular 32 303.70 99 14624.36 1.373
Performance parameters Standard Modular Complete hybrid
Number of slices 19 18 23 19 Complete 32 321.82 111 15220.04 0.630
Number of Flipflops 32 32 32 32 Hybrid 32 300.28 98 14478.52 1.188
Number of 4 input LUTs 33 32 41 33 Standard 64 598.50 195 30479.04 1.144
Number of bonded IOBs 67 67 67 67 Modular 64 599.18 195 30098.95 1.373
Numbre of GCLKs 1 1 1 1
Max frquency of Complete 64 637.15 219 32336.79 0.493
operation(GHz) 368.684 509.671 244.987 378.652 Hybrid 64 595.76 194 30538.83 1.188

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Amrita School of Engineering for providing necessary United States of America, 2003.
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teachers for their guidance, advance and encouragement at College, may 2011.
every step of this endeavor.

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