verilog
verilog
• Specifications – The first step is to define what the digital circuit should do, its interface,
and overall structure.
• RTL Description – The Register Transfer Level (RTL) design describes how data flows
in the circuit. At this stage, EDA tools start assisting the process.
• Logic Synthesis – EDA tools convert RTL into gate-level netlists (circuit representation
with logic gates) while ensuring performance constraints.
• Place and Route – The netlist is placed and routed to create the physical layout of the
chip.
• Verification & Fabrication – The design is verified and fabricated into a real IC chip.
2) Design Methodologies (Hierarchical Modeling Concepts)
• In a top-down design methodology we define the top-level block and identify the sub-
blocks necessary to build the top-level block.
• We further subdivide the sub-blocks until we come to leaf cells, which are the cells that
cannot further be divided.
• Figure 2-1 shows the top-down design process.
In a bottom-up design methodology, we first identify the building blocks that are available to us.
We build bigger cells, using these building blocks.
These cells are then used for higher-level blocks until we build the top-level block in the design.
Figure 2-2 shows the bottom-up design process.
3)Evolution of Computer-Aided Digital Design
• Early Designs – Digital circuits were first made using vacuum tubes and transistors.
• Integrated Circuits (ICs) – Logic gates were placed on a single chip, leading to:
• Need for Automation – As circuits got complex, manual design became difficult.
• EDA Tools Emerge – Electronic Design Automation (EDA) tools helped with logic
simulation and verification.
• VLSI Era – Very Large Scale Integration allowed over 100,000 transistors per chip,
making manual testing impossible.