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I/O Techniques

The document discusses three I/O techniques: Programmed I/O, Interrupt-driven I/O, and Direct Memory Access (DMA). Programmed I/O involves the CPU directly controlling I/O operations with limitations on speed and CPU occupancy, while Interrupt-driven I/O allows the CPU to process other tasks and handle I/O events via interrupts, improving efficiency but still facing speed constraints. DMA is suggested as a more efficient method for transferring large volumes of data, minimizing CPU involvement in the process.

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8 views5 pages

I/O Techniques

The document discusses three I/O techniques: Programmed I/O, Interrupt-driven I/O, and Direct Memory Access (DMA). Programmed I/O involves the CPU directly controlling I/O operations with limitations on speed and CPU occupancy, while Interrupt-driven I/O allows the CPU to process other tasks and handle I/O events via interrupts, improving efficiency but still facing speed constraints. DMA is suggested as a more efficient method for transferring large volumes of data, minimizing CPU involvement in the process.

Uploaded by

haminhtx
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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I/O Techniques

- Programmed I/O
- Interrupt-driven I/O
- Direct memory access (DMA)

7.3. Programmed I/O


1. Basic operation:
+ The CPU directly controls the I/O module by issuing commands
and then waiting until the device completes its operation.
+ Data transfers occur between the processor and the I/O module
through explicit control, meaning the CPU continuously polls the device
to check its status.
2. I/O Commands:
+ Control: used to activate a peripheral and tell it what to do
+ Test: used to test various status conditions associated with an I/O
module and its peripherals
+ Read: causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer
+ Write: causes the I/O module to take an item of data from the data
bus and subsequently transmit that data item to the peripheral

3. I/O Instructions: the CPU uses specific I/O instructions to manage


data exchanges with peripheral devices. These instructions can be
categorized based on how the I/O devices are mapped into the system's
address space:

4. I/O Mapping:
+ Memory-mapped I/O +Isolated I/O (Port-Mapped I/O)

-Shared Address Space:Devices -Separate Address Space:I/O


and main memory share the same devices use a dedicated address
address space. space distinct from main memory.
-Uniform Access:I/O operations -Select Lines Required:Specific
appear as ordinary memory I/O or memory select lines are
read/write operations; no special necessary to differentiate between
I/O commands are needed. memory and I/O operations.
-Instruction Variety: -Specialized Commands:Uses a
A wide variety of standard memory limited set of special commands
access instructions can be used to dedicated to I/O, rather than the full
interact with I/O devices. range of memory access
instructions.

5. Disadvantages:
+ Data transfer speed is limited by the CPU speed.
+ The CPU is occupied with controlling I/O.

7.4 Interrupt-driven I/O


1. Basic Operation:

 The CPU issues an I/O command and continues processing other


tasks instead of waiting for the operation to complete.
 Once the peripheral device has finished its task, it sends an
interrupt signal to the CPU.
 The CPU then temporarily suspends its current activities to execute
an interrupt service routine (ISR), which handles the I/O event.
***Two design issues arise in implementing interrupt I/O:

- Because there will be multiple I/O modules how does the processor
determine which device issued the interrupt?

- If multiple interrupts have occurred how does the processor decide


which one to process?

==> 2. Techniques for Handling Interrupts and Identifying the


Interrupt Source:

 Multiple Interrupt Lines:


o Each device (or group of devices) may have its own
dedicated interrupt line, enabling the CPU to immediately
recognize the source.
 Software Poll:

o After receiving an interrupt, the CPU sequentially checks


each device to determine which one caused the interrupt,
though this method can be time-consuming.

 Daisy Chain (Hardware poll, vectored):

o Devices are connected in series; when multiple devices share


a single interrupt line, the signal passes along the chain with
a unique vector (address) that directs the CPU to the
appropriate ISR.

 Bus Arbitration(vector):

o Before issuing an interrupt, a device must first gain control


of the system bus. Once the CPU acknowledges the
interrupt, the device transmits its vector via the data lines.

3. Examples:

o Devices such as the Intel 82C59A interrupt controller and


the Intel 82C55A programmable peripheral interface are
commonly used to manage and distribute interrupts
efficiently.
Intel 82C59A interrupt controller

Intel 82C55A programmable peripheral interface


4. Advantages:

o Minimizes the CPU’s idle time by eliminating the need for


constant polling, thereby increasing overall efficiency.

5. Disadvantages:

- The I/O transfer rate is limited by the speed with which the
processor can test and service a device

- The processor is tied up in managing an I/O transfer; a


number of instructions must be executed for each I/O transfer

==> When large volumes of data are to be moved a more


efficient technique is direct memory access (DMA)

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