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102 Digital Electronics (Theory) ENGINEERS ZONE

Read Only Memory (ROM)
HAMING CODE
ROM is essentially a memory device in which per
manent binary information is stored.

K inputs
(address)
2xn
ROM
(data)
noutputs
9 AND HAZARDS
In General, a 2Nx n ROM will have an internal K x Error detection and correction
2N decoder and n OR gates.
Consider for example a 32 x 8 ROM The complexity level fo a memory array rnay cauy.
occasional error in starting and retrivening thr.
binary information.
Decoder
x32
5 The most common error detecting scherne is the
2
3 parity bit.
Haming code:
S
6 One of the most common error-correcting codes
used in random-access memories was devised br
28
29
R.W. Hamming.
30 2k -12n+K
31
2k -1-K2n
Where Kparity bits are added to an n-bit data word
forming a new word of n+ Kbits.
A, A, A, A, A, A, A, A
Range of data bits for K check bits
Internal logic of a 32 x 8 ROM
Number of Range of Data bits, n
A, (1,1,1,1,1,)=X(4,3,6, 29, 30) Check bits, K
A4, (11,111,) =(0,3, 28, 31) 3 2 -4
Combinational PLDs 4 5- 11
Acombinational PLD is an integrated circuit with 5 12 - 26
programmable gates divided in to an AND array 6 27- 57
and an OR array to provide and AND-OR sum of
product implementation. Haming code is a type of error correction code.
Fixed And
Multiple extra correction code that not only pro
Programmable vide a detection of bit error but also identify a bit
Array Or Array
Input (Decoder) |Output error.

Prograrnmable Read - Only Many (PROM) Principle of construction of Hamming code:

(i) Howmany parity bits are required?
Programmable Fixed Or
(ii) Where they are to be placed them?
Input Or Array Array Output
(ii) What will be the value of parity bits?
Programmable Array Logic (PAL) #Range of data bit for K check bit
Programmable K
And Array Programmable Range of n
Input Or Array |Output 3
2- 4
4
Prograrmmable Logic Array (PLA) 5- 11
5
12 - 26
6
27- 57
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Digital Electronics (Theory) 103

# Placenment of parity bits

parity bit place at the We obtajn the 12-bit composite word stored in
position at 2 i.e.
memory
2°,2',2', 2' 1 2 3 4 5 67 89 10 11 12
1, 2, 4, 8, .... 0 0 1 1 10 0J 0 1
petermining the value of parity When the 12 bits read from mernory, then check
#p is such that establish even again
parity in position The 4-bit check are evaluated as follows:
20,3, 5, 7, 9, 11, 13, 15, ...
P. XOR of bits (3, 5, 9, 11) C, =XOR of bit (1, 3, 5, 7, 9, 11)
#P, is such that establish even parity in
position C, =XOR of bit (2, 3, 6, 7, 10, 11)
2', 3, 6, 7, 10, 11, 14, 15, ...
P, = XOR of bits (3, 6, 7, 10, 11) C, = XOR of bit (4, 5, 6, 7, 12)
#P. is such that establish even parity in C = X0R of bit (8, 9, 10, 11, 12)
position
22, 5, 6, 7, 12, 13, 14, 15, If C= C,C,C,C, = 0000, no error
P, = X0R of bits (5, 6, 7, 12)
#P, is such that establish even parity in position C=1001, error in 9th bit

23,9, 10, 11, 12, 13, 14, 15, 24, 25, 26,27, 28, 29, Single error correction, double - error detection
30, 31, ... If C=0 and P=0, no error
P, = X0R of bits (9, 10, 11, 12)
If C0 and p=1, Single error, that can be cor
rected
Example: If message 0100, find number of parity If C+ 0 and P=0, Double error, that can detected
and parity bit also write procedure but not corrected.

P P, M, P, M, M M, HAZARDS
1 Hazards are unwated switching transisient that
may appear at the output of a circuit because
Number of message bit = 4 different paths exhibit different propagation delay.
Nurnber of parity bit =3 In combinational circuit it gives temporary false
P = M, M, M, M, =1 output whereas asynchronous sequential cirçuits,
it may result in a transition to a wrong stable state.
P = M, M, M, = 0 Three types Hazards occurs in combinational
circuit
P, = M, M, M, =1 (i) Static 1- Hazards
Consider an other example 8-bit data word
(ii) Static 0 - Hazards
11000100
(ii) Dynamic Hazards
Bit position:
(1) Static 1- Hazards
PP M, P, M, M, M, P, M, Myo M, Mi2 Static 1-Hazards may occurs two AND-OR network.
1 1
1
P=0
P =0

P, =1 Fig.: Static 1-Hazard

P, =1

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