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The document contains a workbook focused on digital electronics, specifically discussing TTL circuits and their operations, including NAND and X-OR gates. It provides various questions and answers related to transistor states and circuit behavior under specific conditions. Additionally, it includes contact information for the organization and a website link.

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3 views2 pages

LF 4

The document contains a workbook focused on digital electronics, specifically discussing TTL circuits and their operations, including NAND and X-OR gates. It provides various questions and answers related to transistor states and circuit behavior under specific conditions. Additionally, it includes contact information for the organization and a website link.

Uploaded by

rampratap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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IESI GATE| PSUs

ENGINEERS
Zono Excollonce ZONE
of for
Englnoors Dlgital Electronics (Workbook) 41

(d) A·(B+C)
(d) T: Active;

STATEMENT
36 & 37: FOR THE LINKED
QUESTION
T:Saturation;

T,: Cut off;


Consider TTL 2-i/P NAND gate given
VBE. actie =0.7V T,: Saturation
37. The voltage V,, is equal to
VEB, sat =0.8V
(a) 0.2 V
VcE. Ssat 0.2V for each transmitor (b) 5 V
(c) 1.4V
V=+ 5V (d) 1.0 V
38. Draw the circuit ofa 2-input X-OR gate using
Ru, (4k)Re= (1.4k)R= (1002) CMOS transistors and explain its operation.
39. The TTL Circuit shown in the figure is fed
with the waveform X (also shown). All gates
have equal propagation delay of 10 ns. The
output Y if the circuit is

¿R= (1k)
100 ns
1

36. When A=B=1 (i.e. +5V); the states of the


different transitors are
X
(a) T : Inverse active;

T,: Saturation;
T,: Saturation;
T,:Saturation
(b) T: Inverse active;
T, : Saturation; (a) 1

T, : Cut off;
T,: Saturation

(c) T,: Active;


T, : Cut off;
T,: Saturation; (b)

T,: Saturation

Regd. office: 65/C, Prateek Market, Near Canara Bank, Munirka Market,
etat No: 011-26194869, 9873000903, New Delhi-110067
9873664427, 8860182273; Website: www.ghengineerszone.com
IESI GATE |PSus
Digital Electronics (Workbook) ENGINEERS ZONE
Zone of Excellence for
42 Engineere

4. Ans: (d)

Y 5. Ans: (d)
6. Ans: (c)
7. Ans: (a)
8. Ans: (c)
(c)
9. Ans: (c)
t 10. Ans: (a)
11. Ans: (c)
Y
12. Ans: (a)
13. Ans: (c)
14. Ans: (b)

(d) 15. Ans: (b)


16. Ans: (a)
t 17. Ans: (b)
18.
40. A TTL NOT gate circuit is shown in figure.
Assuming Va =0.7 V of both the transitors, 19. Ans: (c)
20.
if V, = 3.0 V, then the states of the two
21. Ans: (c)
transitors will be
22. Ans: (a)
23. Ans: (d)
+5V
4 kQ 1.6 kQ2 24. Ans: (d)
25. Ans: (d)
26. Ans: (c)
27. Ans: (b)
28. Ans: (d)
29. Ans: (a)
30. Ans: (d)
(a) , ON and Q, OFF 31. Ans: (b)
32. Ans: (d)
(b) @, reverse ON and Q, OFF
33. Ans: (b)
(c) , reverse ON and Q, ON 34. Ans: (a)
35. Ans: (a)
(d) Q, OFF and Q, reverse ON
36. Ans: (b)
37. Ans: ()
38.
ANSWERS
39. Ans: (a)
40. Ans: (c)
1. Ans: (a)
2 Ans: (b)
3. Ans: (a)

Regd. Office: 65/C, Prateek Market, Near Canara Bank, Munirka Market, New Delhi-110067
Contact No: 011-26194869, 9873000903, 9873664427, 8860182273; website: www.ghengineerszone.com

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