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Assignment 4

The document outlines Assignment 4 for the EE719 Mixed-Signal VLSI Design course at IIT Bombay, focusing on the design of a StrongARM Latch with specific parameters and design procedures. Students are instructed to use GPDK 45nm MM CMOS technology and to follow a structured design process involving initial calculations, simulations, and iterations to meet specified performance metrics. The assignment includes detailed guidelines on simulation setup, design variables, and expected output waveforms.

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9 views3 pages

Assignment 4

The document outlines Assignment 4 for the EE719 Mixed-Signal VLSI Design course at IIT Bombay, focusing on the design of a StrongARM Latch with specific parameters and design procedures. Students are instructed to use GPDK 45nm MM CMOS technology and to follow a structured design process involving initial calculations, simulations, and iterations to meet specified performance metrics. The assignment includes detailed guidelines on simulation setup, design variables, and expected output waveforms.

Uploaded by

rahul23.techfest
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE719 : Mixed-Signal VLSI Design, 2024-25/Spring

Dept. of Electrical Engineering


IIT Bombay

Assignment 4
Total Marks: 20
Submission Deadline: 8 pm, Monday, 24th March, 2025
Refer the Tutorial-7 for guidance
General Instructions:
1. Set up the simulation options and accuracy presets to be the same as those used in the
first assignment. Include a snapshot of the options at the beginning of your submission.
2. Use nmos2v and pmos2v device from GPDK 45nm MM CMOS technology
for simulations, VDD = 1.5V, VSS = 0V.
3. Connect the body of NMOS transistors to VSS.
4. For design procedure you may refer the below mentioned papers.
(a) Design procedure discussed in class and tutorial-7.
(b) The StrongARM Latch: B. Razavi, “The StrongARM Latch [A Circuit for All Sea-
sons]”, 2015
(c) The Design of a Comparator: B. Razavi, “The Design of a Comparator [The Analog
Mind]”, 2020
5. Since it is a design problem, you may have to go under iterations to achieve the desired
specifications. So, while finding the design variables, you would start with hand calcula-
tions and then fine-tune the values to achieve the specification through simulations.

1 Problem Statement
In this assignment, we will design a StrongARM Latch.

(a) Output Waveforms (b) Clock Waveform

Figure 1: Timing Diagram

1
Parameter Value
Supply Voltage(VDD ) 1.5
Input Voltage Range (VF S ) 0.7 − 1.3V
Temperature 27◦ C
Sampling Frequency (fs ) 500 M Hz
Clock Rise/Fall time 20 ps
Input Referred Offset
(Only for the purpose of estimating < 2 mV
minimum area of M1,2 of the comparator)
Load Capacitance(CL ) 10 f F
Logic Levels High:1.1 V , Low:0.4 V
Max(t1 ,t2 ) [Refer Figure 1a ] < 500 ps

Table 1: Specification for StrongARM Latch

Consider the specifications below in Table 1 below. For hand calculation, take AVth =
3mV · µm (Mismatch in input transistor is also considered by taking high values of AVth ).

Figure 2: StrongArm Latch Comparator

2 Initial Design Procedure


Refer to Figure 2. You have to design this comparator and provide a design procedure.
Design of StrongARM Latch
1. Find the initial width and length of transistors M7 . [2]
2. Consider practical initial values for C1,2 and C3,4 . [1]
3. Find the initial width and length of transistors M1 and M2 . [2]
4. Find the initial width and length of transistors M3 and M4 . [2]

2
5. Find the initial width and length of transistors M5 and M6 . [2]

6. Find the initial width and length of transistors S1−4 . [2]

7. Tabulate the widths and lengths of transistors in the table below. [2]

Design variable (Initial Values) M1 M2 M3 M4 M5 M6 M7 S1 S2 S3 S4


Width
Length

Table 2: Initial width and length of transistors

8. Simulate the circuit and get values of t1 and t2 from simulation. If you have overdesigned,
reduce the assumed initial value of C1,2 and C3,4 . Go back to the initial design step
and repeat the design process (you can use values of transistor capacitor obtained from
simulation, refine your initial assumption ) [3]

Design variable(Final Values) M1 M2 M3 M4 M5 M6 M7 S1 S2 S3 S4


Width
Length

Table 3: Final width and length of transistors

3 Transient Output
In this section, we will observe waveforms at various nodes. keep Vref = 0.9 , and provide a
ramp at the other input with a rate of 0.5 mV per cycle, simulating for a few cycles.

1. Provide waveforms at each node Vd1 , Vd2 ,Vout+ , and Vout− with respect to clock. Provide
the input as shown in Figure 3. It is important to report the waveform not from t=0 but
to leave some cycles and then report it. Annotate and label the waveform of Vout+ , and
Vout− with t1 and t2 time instances as shown in figure 1(a). (Plot time on X-axis and
voltage on Y-axis) [4]

Figure 3: Input to comparator

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