University of Dubai

College of Engineering and IT

Department of Electrical Engineering

Digital Logic Design (ENDD 200)

Lab Manual

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

Spring 2023-2024
Contents
Experiment (1): Introduction to Basic Logic Gates.................................................................................3
Experiment (2): Exploring Possibilities With Logic Gates.......................................................................7
Experiment (3): Logic Gate Applications.............................................................................................11
Experiment (4): Parity Check with Logic Gates....................................................................................15
Experiment (5): Adder & Subtractor Logic Circuits..............................................................................18
Experiment (6): Decoders & Multiplexers...........................................................................................23
Experiment (7): Introduction to Flip Flops...........................................................................................28
Experiment (8): Problem solving with K-maps....................................................................................31
Experiment (9): Logic Circuit Design with PoS method........................................................................34
Appendix............................................................................................................................................35
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

Digital Logic Design (ENDD 200)

Laboratory Experiment No.1

Experiment Title: Introduction to Basic Logic

Gates

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

CLO1 Identify and use the binary and hexadecimal number Lab report /1
systems and signed arithmetic.
Total /1

Risk Assessment: Low

Introduction
A logic gate is a device that acts as a building block for digital circuits. They perform basic logical functions
that are fundamental to digital circuits. Most electronic devices we use today will have some form of logic
gates in them. For example, logic gates can be used in digital electronics such as smartphones and tablets
or in memory devices.

The basic logic gates are categorized into seven types as AND, OR, XOR, NAND, NOR, XNOR, and NOT.

In this Lab, the students use Multisim software to implement the circuits. Multisim Electronics Workbench
is industry-standard SPICE simulation and circuit design software for analog, digital, and power electronics
in education and research.

Task 1: Boolean logic (10 points each)

What is the truth table for an AND gate?

Input 1 Input 2 Output

What is the truth table for an OR gate?

Input 1 Input 2 Output

Imagine that an AND gate has three inputs instead of two. What would be its truth table?
 Input 1 Input 2 Input 3 Output

Imagine that an OR gate has three inputs instead of two. What would be its truth table?

Input 1 Input 2 Input 3 Output

Task 2: Circuits and Simulations (20 points each)

Create the following designs using Multisim:

1. Use an AND gate to switch an LED on and off. Provide screenshots of your work.
2. Use an OR gate to switch an LED on and off. Provide screenshots.
3. Insert an Inverter between the output of the OR gate and the LED. Write down the resulting truth
table.

Input 1 Input 2 Output

Task 3: Experimental implementation

1. Connect the circuit in Task2 (AND/ OR) on the bread board by using the below components, take
photos for the final design and include them in your reports (Refer to Pin configuration in the appendix).
• DC voltage source -5V

• LEDs

• IC74LS08 (Refer to the IC 741LS08 Datasheet in the appendix)

• IC74LS32 (Refer to the IC74LS32 Datasheet in the appendix)

• Wires
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

Digital Logic Design (ENDD 200)

Laboratory Experiment No.2

Experiment Title: Exploring Possibilities with Logic

Gates

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

CLO1 Identify and use the binary and hexadecimal number Lab report /1
systems and signed arithmetic.
Total /1

Risk Assessment: Low

Introduction
A logic gate is a device that acts as a building block for digital circuits. They perform basic logical functions
that are fundamental to digital circuits. Most electronic devices we use today will have some form of logic
gates in them.
In this lab the students will investigate the behavior of many types of logic gates with many inputs 2, 3,
4,etc.

Task 1: Possible combinations (10 points each)

1. How many possible input combinations are there for a 3-input AND gate?

2. How many possible input combinations are there for a 4-input AND gate?

3. If you have a 2-input AND gate, and a 2-input OR gate with their outputs connected to another 2-
input OR gate. How many possible input combinations are there in total?

Task 2: Circuit building with Multisim. (20 points each)

1. In multisim, insert a 2-input NAND gate. Experiment with all possible inputs and write down the
full truth table for the device.

2. Design an equivalent NAND gate circuit without using an NAND gate. Instead, use two types of the
basic logic gates: AND/OR/Inverter. Which logic gates will you use? How will they be connected?
 3. Recreate the following (OR gate + Inverter) circuit and answer the questions that follow:

a. Write down the full truth table for the circuit.

Input 1 Input 2 Output

b. Insert a second inverter after the first inverter. What would be the simplified equivalent circuit?

2. Recreate the following (AND gate + Inverter) circuit and answer the questions that follow:

a. Write down the full truth table for the circuit. Use the table below

Input 1 Input 2 Output

b. Insert a second inverter after the first inverter. What would be the simplified equivalent circuit?
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

Digital Logic Design (ENDD 200)

Laboratory Experiment No.3

Experiment Title: Logic Gate Applications

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

CLO2 Simplify Boolean functions using Karnaugh maps and Lab report /0.5
Boolean algebra.
Total /0.5

Risk Assessment: Low

Introduction

The range of usage of logic gates is quite extensive, such as in manufacturing more complex devices e.g.
binary counters, in decision–making regarding automatic control of machines and different industrial
processes, in calculators and computers, in digital measuring techniques, in digital processing of
communications, in musical instruments, games and different domestic appliances

Task A: Applications of Logic Gates (Simulation using Multisim)

You have successfully found a job as a circuit designer at RLD systems. RLD is a local start-up company.
It specializes in building circuit boards for security and lighting systems. Your first task is to build an alarm
system for use in a school environment.

4. The school has been having issues with water leakage in its water storage system. Usually, it is
either a loose tank lid or damage to a transmission pipe that lead to such leakage. Create a circuit
that lights a Red LED if any one of these two reasons is detected.
5. The school has a problem with strangers trespassing into school premises. In particular, the recess
and school bus parking areas are the center of such occurrences. There are now cameras in both
areas to detect strangers. Create a circuit that sounds a Buzzer if a trespasser is detected in any of
these two areas.
6. As a side task, the school also wishes to have a buzzer that switches on only after the first three
classes have ended. This is needed to let students know that recess time has started.

7. Observe the following:

 a. Design the circuit in multisim and write down its truth table.

z
 b. Can you use only one logic gate instead of two to arrive at the same truth table? If so what
would be the equivalent circuit?
YES WE Can represent by OR gate.
Task B: Applications of Logic Gates (Experimental implementation)

1. Repeat steps 1-3 by construct the circuit on the bread board by using the below components,
take photos for the final design and include them in your reports (Refer to Pin configuration in
the appendix).
 DC voltage source -5V
 LEDs
 IC74LS08 (Refer to the IC 741LS08 Datasheet in the appendix)
 IC74LS32 (Refer to the IC74LS32 Datasheet in the appendix)
 Wires

Pin diagram of IC74LS32

Pin diagram of IC74LS08
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

Digital Logic Design (ENDD 200)

Laboratory Experiment No.4

Experiment Title: Parity Check with Logic Gates

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

CLO2 Simplify Boolean functions using Karnaugh maps and Lab report /0.5
Boolean algebra.
Total /0.5

Risk Assessment: Low

Introduction

When a stream of bits is sent from one point to another within a single digital system or from one
system to another, errors may occur. Wireless communication systems experience errors in data
transmission. Errors take the form of bit changes from “0” to “1 “or vice versa. Many systems, however,
employ something called a “parity” bit as a means of detecting bit errors. Binary information is normally
handled by a digital system in groups of bits called words. A word always contains either an even or an odd
number of 1's. An even parity bit makes the total of “1’s” even.

Say that you want to transmit 4 bits, and the number of “1’s” is even in the 4 bit word. The Even
parity checker ensures that there is an even number of “1’s” by giving a parity bit of zero if there is an even
number of “1’s”. An odd parity checker ensures that there is an odd number of “1’s” by giving a parity bit
of “1” if there is an even number of “1’s” in the word.

Let us demonstrate this by example:

10100 gives an even parity of 0

10110 gives an even parity of 1

10100 gives an odd parity of 1

10110 gives an odd parity of 0

But how can we implement this concept for error checking in hardware?

We can use logic gates to do so. One way of doing so, is to use XOR gates. In your first task. You shall
explore the function of the XOR gate and its truth table. In the second task, you will implement a parity
checker using XOR gates.

Task 1: The XOR Logic Gate (10 points each)

1. In multisim, insert a two-input XOR gate and connect it to a digital state meter to detect the
output for all possible combinations of inputs. Take a screenshot for your configuration
 2. Write down the truth table for the two-input XOR gate.

Task 2: Parity Checker Design (20 points each)

In order to check for or generate the proper parity in a given code word. The sum of an even number
of 1's is always zero, and the sum of an odd number of 1's is always one.

1. Create a three-bit even parity checker and write down its truth table.
2. Create a three-bit odd parity checker and write down its truth table.
0
3. Create a four-bit even parity checker and write down its truth table.

4. Create a four-bit odd parity checker and write down its truth table.
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

ENDD 200 Digital Logic Design Laboratory

Experiment No.5

Experiment Title: Adder & Subtractor Logic Circuits

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

CLO3 Create combinational logic circuits and systems. Lab report /2
Total /2

Risk Assessment: Low

Introduction:
Previously we used XOR gates to create parity check circuits. The concept utilized Boolean arithmetic to
find odd and even numbers of 1’s for a given sequence of binary digits.

This time, we will use XOR gates alongside other kinds of logic gates to create addition and subtraction
operations.

Adders

Half-Adders: A half-adder does binary addition on two inputs (A and B).

The two outputs are labeled sum (S) and carry (C). Half adders can be built with:
An XOR gate and an AND gate (shown on the left). A component in Multisim (shown on the right).

Half Adder with gates Half Adder symbol

Full-Adders: A full-adder does binary addition on three inputs: A, B, and Cin.

Full adders usually work in a cascade fashion where they are used to add binary numbers with an
increasing number of bits. The two outputs are sum (S) and carry (Cout). You will notice that full adders
can also use logic gates or a component.

Full Adder with Gates Full Adder Symbol

TASK 1: Half-Adder Circuit

 1. Open Multisim
2. Construct the circuit given below
3. Test all possible input combinations and write down the full truth table for the circuit.

A B SUM CARRY

0 0

0 1

1 0

Half Adder Circuit 1 1

TASK 2: Full-Adder Circuit

1. Open Multisim
2. Construct the circuit given below
3. Test all possible input combinations and write down the full truth table for the circuit.

Full Adder Circuit

 A B C SUM CARRY

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

TASK 3: Half-Subtracter Circuit

A subtracter circuit is similar to adder circuit with a slight change. It uses inverters to come up with
difference and borrow values. Construct the circuit below and write down its full truth table.

A B XOR AND
DIFF BORROW

0 0

0 1

1 0

1 1

Half Subtracter Circuit

TASK 4: Full-Subtracter Circuit

1. Open Multisim
2. Construct the circuit given below
3. Insert 2 XOR gates, 2 NOT gates, 1 OR gate and 2 AND gates.
4. Insert 3 DIGITAL CONSTANTs.
5. Test all possible low and high conditions for inputs and record your results
6. Compare your sum and carry results with manual calculation

Full Subtracter Circuit

A B C DIFFERENCE BORROW

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

ENDD 200 Digital Logic Design Laboratory

Experiment No.6

Experiment Title: Decoders & Multiplexers

Instructors: Eng. Eman Abu Shabab &Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

4 Analyze the operation and use of /2
combinational building blocks, such as
multiplexers, decoders, and encoders.
Total /2

Risk Assessment: Low

Introduction

The Multiplexer (MUX) is a device that allows one or more low-speed analog or
digital input signals to be selected, combined and transmitted at a higher
speed on a single shared medium or within a single shared device.

The Binary Decoder is another type of digital logic device that has inputs of 2-bit, 3-
bit or 4-bit codes depending on the number of data input lines. A decoder that has a
set of two or more bits will be defined as having an n-bit code, and therefore it will
be possible to represent 2n possible values. Thus, a decoder generally decodes a
binary value into a non-binary one by setting exactly one of its n outputs to logic
“1”.
Task 1-A (Simulation using Multisim)
 Design a 4-1 multiplexer. Provide screenshots and a truth table to verify your
results.

Fig.1
Task 1-B (Hardware implementation)
 Connect a 4-1 multiplexer as per Fig.2 Using IC 74151, LED, on the bread
board. The multiplex function of 74151 in terms of select lines is shown in the
table below. (Refer to the DM74ALS151 1 of 8 Line Multiplexer Datasheet in
the appendix)
 Fig.2

 Provide screenshots and a truth table to verify your results.

Task 2
Design a 2-4 decoder. Provide screenshots and a truth table to verify your results.

A B Q0 Q1 Q3 Q4
0 0
0 1
1 0
1 1

Fig.3

Task 2-B (Hardware implementation)

  Connect a 2-4 decoder as per Fig.4 Using IC 74139, LED, on the bread board.
(Refer to the 74HC/HCT139 Datasheet in the appendix)

Fig.4

 Provide screenshots and a truth table to verify your results.

 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

ENDD 200 Digital Logic Design Laboratory

Experiment No.7

Experiment Title: Introduction to Flip Flops

Instructors: Eng. Eman Abu Shabab &Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

5 Analyze and design sequential logic /2
circuits and systems using flip flops and
the finite state machine design
methodology
Total /2

Risk Assessment: Low

Task 1: Pre-lab
Implement the following Boolean algebra statements in circuit form using Multisim.
Then, fill their corresponding truth tables.

1- AB’ + AB

2- (AB)’ + A’B

3- (AB)’ + (AB)’

Task 2: Introduction to D-type Flip Flops

We will use NAND gates to implement a circuit that remembers a previous state
(previous output). We will see how this is possible using an inverter and and 4
NAND gates.

To do so, recreate the following circuit in Multisim.

1- Take 2 or 3 screenshots for your design and show the resulting time plot for
different input states.

2- Investigate the role of the second (lower) input labeled as DG2 in the above
schematic. (40 points each)
(a) To do so, fill in the following Truth table.

DG1 DG2 LED1 LED2

(b) Comment on how the output depends on the state of DG2.

 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

ENDD 200 Digital Logic Design Laboratory

Experiment No.8

Experiment Title: Problem solving with K-maps

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

2 Simplify Boolean functions using /0.5
Karnaugh maps and Boolean algebra.
Total /.5

Risk Assessment: Low

Introduction:

In many digital circuits and practical problems, we need to find expression with minimum variables. We
can minimize Boolean expressions of 2, 3, or 4 variables very easily using the K - map without using any
Boolean algebra theorems. The K -map can take two forms Sum of Product (SOP) and Product of Sum (POS)
according to the needs of the problem. The K -map is table-like representation but it gives more
information than TRUTH TABLE. We fill the grid of K - map with 0’ s and 1’ s then solves it by making
groups.

Task A: Job Statement

A sewage treatment plant has recently hired you to help with the automation of their operations. One of
their onshore sewage dispensers, releases sewage into the sea. In order to sanitize the sewage before it is
discharged into the sea, a disinfectant is applied to the sewage. Given the hazardous nature of this
operation, you were tasked with designing a logic circuit that allows the dispenser to discharge sewage
only if the disinfectant is being sprayed in the discharge pipe. If there is no disinfectant being sprayed in
the pipe, then the dispenser lid should close and not let any sewage pass into the pipe.

Hence, it is required to have 3 sensors to sense the presence of the disinfectant gas. This number of
sensors is needed in the case of a single sensor failure. The lid of the dispenser would open only if at least
two sensors sense that the disinfectant is present in the pipe; otherwise, the lid would close and no
sewage would be let out from the dispenser.

As a digital designer, you are tasked with creating a solution for this problem. You should write a truth
table for proper logic circuit operation of the sensors and their output. Note that each sensor represents
one input. Each sensor detects whether the disinfectant is being sprayed (logic level “1”) or not (logic level
“0”). You should then design hardware circuitry using logic gates. Refer to the following steps to complete
the task.

1- Write down the truth table. There are three inputs and one output (open lid = 1).

2- Write down the Boolean algebra expression for the truth table. Use the Sum-of-Products (SoP)
method.

3- Implement the circuit using logic gates based on the Boolean expression.

4- Now write down a k-map for the same truth table.

5- Use the k-map to arrive at a simplified Boolean expression.

6- Implement the circuit using logic gates using Multisim

7- (Hardware implementation): Implement the circuit on the breadboard using the required
Logic gates/ICs and LED, replace the sensors with switches.
 University of Dubai
College of Engineering and IT
Department of Electrical Engineering

ENDD 200 Digital Logic Design Laboratory

Experiment No.9

Experiment Title: Logic Circuit Design with PoS

method

Instructors: Eng. Eman Abushabab & Dr. Yasmin Halawani

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

2 Simplify Boolean functions using /0.5
Karnaugh maps and Boolean algebra.
Total /.5

Risk Assessment: Low

Introduction:
POS stands for product of sum is a technique of explaining a Boolean expression through a set of max
terms or sum terms.
The Difference between the SOP and POS in Digital Logic is that the SOP includes the OR of multiple
product terms. POS, on the other hand, generates a logical expression composed of the AND of multiple
OR terms. The SOP (Sum of Product) and POS (Product of Sum) methods are used to deduce a specific logic
function.

Task: Circuit implementation using Boolean Expressions

Given the following truth table:

1- Use the Product of Sum (PoS) method to arrive at a Boolean algebra expression to represent the
truth table.
2- Implement the expression in a digital circuit form.

3- Now write down a k-map for the same truth table.

4- Use the k-map to arrive at a simplified Boolean expression.

5- If possible, Implement the simplified circuit using logic gates.

Appendix
 Assessment Instrument Cover Sheet

Course Code: ENDD 200 Course Title: Digital Logic Design

Semester: Spring 2024 Academic year: 2023/2024
Assessment Instrument: Lab Project Due Date:

This instrument assesses the following Course Learning Outcomes (CLO):

CLOs Course Learning Outcomes (CLO)* Criteria Marks

6 Simulate logic circuits and interpret Lab Project Presentation /10
experimental data and relate it to the and report
theory.

Total

ENDD200 Lab Project Evaluation

Student Name
1.
2.
3.
4.

Student ID:
1.
2.
3.
4.

Rubric for Project Report Evaluation Maximum Marks: 40

Excellent (10) Good Average Poor Score
a Project - Project report - Project report - Project - Project
Report is according is according report is report not
to the given to the given according to prepared
format format the given according
- References - References format but to the
and citations and citations some given
are are mistakes format
appropriate appropriate - In-sufficient - Reference
and well but not references s and
mentioned mentioned and citations citations
well are not
appropriat
e
Excellent (10) Good Average Poor Score
b Description - Complete - Complete - Incomplete -
of explanation explanation explanation Inappropriat
Concepts of the key of the key of the key e
and concepts and concepts but concepts explanation
Technical strong in- sufficient and in- of the key
Details description of description of sufficient concepts
the technical the technical description and poor
requirements requirements of the description
of the project of the project technical of the
requirement technical
s of the requirement
project s of the
project
Excellent (20) Good Average Poor Score
c Results, - Results and - Results and - Results and - Results
Discussion calculation calculations calculations and
and are presented are presented calculatio
conclusion in very presented in are not ns are not
appropriate good manner much presented
manner - Project work satisfactory properly
- Project work summary and - Project work - Project work
is well conclusion summary is not
summarized not very and summarized
and appropriate conclusion and
concluded - not very concluded
appropriate
Rubric for Presentation Evaluation (Max marks 30)
Excellent (15) Good (12) Average (9) Poor (6) Score
Technical
Knowledge Extensive
and knowledge and Fair knowledge Lacks Poor knowledge
d Awareness awareness related and awareness sufficient and no
related to the to the project related to the knowledge awareness
Project project and related to
Awareness project
Contents of Contents of Contents of
Contents of
presentations are presentations are presentations
presentations
e Presentation appropriate and appropriate and
are appropriate
are not -
well delivered in well delivered in appropriate
but not well
clear voice with clear voice with and not well
delivered;
good spoken good spoken delivered;
unclear voice
language language unclear voice
Lab Project / Phase (1) –Proposal Evaluation Maximum Marks: 30
1.
2.
3.
4.

Total Marks =
(Max 100%)
1.
2.
3.
4.
How to read Data sheet and identify Pins
Datasheets are instruction manuals for electronic components. They explain exactly what a
component does and how to use it, datasheets are the best place to find the details you need to
design a circuit or get one working.
A datasheet’s contents will vary widely depending on the type of part, but they will usually have
most of the following sections:
The first page is usually a summary of the part’s function and features. This is where you can
quickly find a description of the part's functionality, the basic specifications (numbers that
describe what a part needs and can do), and sometimes a functional block diagram that shows
the internal functions of the part. This page will often give you a good first impression as to
whether potential part will work for your project or not.
A pinout lists the part’s pins, their functions, and where they’re physically located on the part for
various packages the part might be available in. Note the special marks on the part for
determining where pin 1 is (this is important when you plug the part into your circuit!), and how
the pins are numbered.
You'll also see the more normal recommended operating conditions in the data sheet. These may
include voltage and current ranges for various functions, timing information, temperature ranges,
bus addresses, and other useful performance information.
Some parts will have one or more graphs showing the part’s performance vs. various criteria
(supply voltage, temperature, etc.) Keep an eye out for "safe zones" where reliable operation is
guaranteed:
Pin Configuration
The pins on an IC chip provide connections to the tiny integrated circuits inside of your
electronics. To determine which pin is which, you look down on the top of the IC for the clocking
mark, which is usually a small notch in the packaging but might instead be a little dimple or a
white or colored stripe. By convention, the pins on an IC are numbered counterclockwise, starting
with the upper-left pin closest to the clocking mark.
74LS08 – Quadruple Two Input AND Gate

74LS08 IC

74LS08
Pinout
74LS08 IC is a member of 74XXYY IC series. There are four AND gates in the
chip and each gate have two inputs, hence the name QUADRUPLE 2- INPUT
AND GATE. The gates in the chip are designed by SCHOTTKY TRANSISTORS for
high speed logic operations.

74LS08 Pin configuration

74LS08 is a 14 PIN IC. The chip is available in different packages and is chosen
depending on requirement. The description for each pin is given below.

Pin Number Description

AND GATE 1

1 A1-INPUT1 of GATE 1

2 B1-INPUT2 of GATE 1

3 Y1-OUTPUT of GATE1

AND GATE 2

4 A2-INPUT1 of GATE 2

5 B2-INPUT2 of GATE 2

6 Y2-OUTPUT of GATE2

AND GATE 3
 9 A3-INPUT1 of GATE 3

10 B3-INPUT2 of GATE 3

8 Y3-OUTPUT of GATE3

AND GATE 4

12 A4-INPUT1 of GATE 4

13 B4-INPUT2 of GATE 4

11 Y4-OUTPUT of GATE4

SHARED TERMINALS

7 GND- Connected to ground

14 VCC-Connected to positive voltage to provide power to all four gates

Features and Specifications

 Operating voltage range: +4.75 to +5.25V

 Recommended operating voltage: +5V
 Maximum supply voltage:7V
 Maximum current allowed to draw through each gate output: 8mA
 TTL outputs
 Low power consumption
 Typical Rise Time: 18ns
 Typical Fall Time: 18ns
 Operating temperature:0°C to 70°C
 Storage Temperature: -65°C to 150°C
 ICs
IC74LS08 Data sheet

August 1986
Revised March 2000

DM74LS08
Quad 2-Input AND Gates
General Description
This device contains four independent gates
each of which performs the logic AND
function.

Ordering Code:

Order Package Package Description

Number Number
DM74LS08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-
120, 0.150 Narrow
DM74LS08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm
Wide
DM74LS08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001,
0.300 Wide
 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Inputs Output

A B Y

L L L

L H L

H L L

H H H
Y=
AB H = HIGH Logic
Level L = LOW Logic
Level

© 2000 Fairchild Semiconductor Corporation DS006347

 Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which

Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be

Input Voltage 7V operated at these limits. The parametric values defined in the
Electrical Characteristics tables are not guaranteed at the absolute maximum
ratings.

Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define
the conditions for actual device operation. Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

TA Free Air Operating 0 70 °C

Temperature

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min (Note Max Units
2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max, V

Output Voltage 2.7 3.4
VIH = Min
VOL LOW Level VCC = Min, IOL = Max, V
Output Voltage 0.35 0.5
VIL = Max

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICCH Supply Current with Outputs HIGH VCC = Max 2.4 4.8 mA

ICCL Supply Current with Outputs LOW VCC = Max 4.4 8.8 mA

Switching Characteristics
at VCC = 5V and TA = 25°C

RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max
 tPLH Propagation Delay Time
4 13 6 18 ns
LOW-to-HIGH Level Output

tPHL Propagation Delay Time

3 11 5 18 ns
HIGH-to-LOW Level Output

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

www.fairchildsemi.com 2
Physical Dimensions inches (millimeters) unless otherwise

14Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-

120, Package Number

3
 Physical Dimensions inches (millimeters) unless otherwise noted

14Lead Small Outline Package (SOP), EIAJ TYPE

II, Package Number

www.fairchildsemi.c 4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no
circuit patent licenses are implied and Fairchild reserves the right at any time
without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS
IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL
OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in
any component of a life support which, (a) are intended for surgical implant into
the device or system whose failure to perform can be reabody, or (b) support or
sustain life, and (c) whose failure sonably expected to cause the failure of the life
support to perform when properly used in accordance with device or system, or
to affect its safety or effectiveness. instructions for use provided in the labeling,
can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

5
IC74LS32 Data sheet

June 1986
Revised March 2000

DM74LS32
Quad 2-Input OR Gate
General Description
This device contains four independent gates
each of which performs the logic OR function.

Ordering Code:

Order Package Package Description

Number Number
DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-
120, 0.150 Narrow
DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm
Wide
DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001,
0.300 Wide
 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Y=A+ B
H = HIGH Logic Inputs Output Level
L = LOW Logic
Level A B Y
L L L
L H H
H L H
H H H

© 2000 Fairchild Semiconductor Corporation DS006361

 Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which

Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be

Input Voltage 7V operated at these limits. The parametric values defined in the
Electrical Characteristics tables are not guaranteed at the absolute maximum
ratings.

Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define
the conditions for actual device operation. Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
TA Free Air Operating 0 70 °C
Temperature

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min (Note Max Units
2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max

Output Voltage 2.7 3.4 V
VIH = Min
VOL LOW Level VCC = Min, IOL = Max
Output Voltage 0.35 0.5
VIL = Max
V
IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICCH Supply Current with Outputs HIGH VCC = Max 3.1 6.2 mA

ICCL Supply Current with Outputs LOW VCC = Max 4.9 9.8 mA

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max
tPLH Propagation Delay Time
3 11 4 15 ns
LOW-to-HIGH Level Output
 tPHL Propagation Delay Time
3 11 4 15 ns
HIGH-to-LOW Level Output

www.fairchildsemi.com 2
Physical Dimensions inches (millimeters) unless otherwise

14Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-

120, Package Number

3
 Physical Dimensions inches (millimeters) unless otherwise noted

14Lead Small Outline Package (SOP), EIAJ TYPE

II, Package Number

www.fairchildsemi.c 4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no
circuit patent licenses are implied and Fairchild reserves the right at any time
without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS
IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL
OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in
any component of a life support which, (a) are intended for surgical implant into
the device or system whose failure to perform can be reabody, or (b) support or
sustain life, and (c) whose failure sonably expected to cause the failure of the life
support to perform when properly used in accordance with device or system, or
to affect its safety or effectiveness. instructions for use provided in the labeling,
can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

5
DATA SHEET
For a complete data sheet, please also download:

 The IC06 74HC/HCT/HCU/HCMOS Logic Family

Specifications
 The IC06 74HC/HCT/HCU/HCMOS Logic Package
Information
 The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT139
Dual 2-to-4 line
decoder/demultiple
xer
Product specification September 1993
File under Integrated Circuits, IC06
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

FEATURES GENERAL DESCRIPTION

· Demultiplexing capability The 74HC/HCT139 are high-speed Si-gate CMOS

· Two independent 2-to-4 devices and are pin compatible with low power
decoders Schottky TTL (LSTTL). It is specified in
compliance with JEDEC standard no. 7A.
· Multifunction capability
The 74HC/HCT139 are high-speed, dual 2-to-4 line
· Active LOW mutually exclusive decoder/multiplexers. This device has two
outputs independent
· Output capability: standard decoders, each accepting two binary weighted
inputs (nA0 and nA1) and providing four mutually
· ICC category: MSI
exclusive active
LOW outputs (nY0 to nY3). Each decoder
has an active LOW enable input (nE).
When nE is HIGH, every output is forced
HIGH. The enable can be used as the data
input for a 1- to-4 demultiplexer
application.
The “139” is identical to the HEF4556 of
the HE4000B family.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
t /t
PHL PLH propagation delay CL = 15 pF; VCC = 5
nAn to nY n V 11 13 ns
nE 3 to nYn 10 13 ns
CI input capacitance 3.5 3.5 pF
C
PD power dissipation capacitance per notes 1 and 2 42 44 pF
multiplexer
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW):
2 2
PD = CPD ´ VCC ´ fi + å (CL ´ VCC ´ fo)
where: fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ CC2 ´ fo) = sum of outputs CL =
V
output load capacitance in pF VCC =
supply voltage in V
2. For HC the condition is VI = GND to
VCC For HCT the condition is VI = GND to
VCC - 1.5 V

APPLICATIONS
· Memory decoding or data-routing
· Code conversion

ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993 2
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 15 1E, 2E enable inputs (active LOW)
2, 3 1A0, 1A1 address inputs
4,5,6,7 1Y 0 to 1Y3 outputs (active LOW)
8 GND ground (0 V)
12, 11, 10, 9 2Y 0 to 2Y3 outputs (active LOW)
14, 13 2A0, 2A1 address inputs
V
16 CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol.

(a (b
) )
Fig.3 IEC logic
symbol.

September 1993 3
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

Fig.4 Functional
diagram.

FUNCTION TABLE

INPUTS OUTPUTS

nE nA0 nA1 nY0 nY1 nY2 nY3

H X X H H H H
L L L L H H H
L H L H L H H
L L H H H L H
L H H H H H L
Notes
1. H = HIGH voltage
level L = LOW
voltage level X =
don’t care

Fig.5 Logic diagram (one decoder/demultiplexer).

September 1993 4
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT V WAVEFORMS
CC
25 40 to 85 40 to 125 (V)
min. typ. max. min. max. min. max.
39 145 180 220 2.0
t /t propagation delay
PHL PLH 14 29 36 44 ns 4.5 Fig.6
nAn to Yn 11 25 31 38 6.0
33 135 170 205 2.0
t /t propagation delay
PHL PLH 12 27 34 41 ns 4.5 Fig.7
nE to nYn 10 23 29 35 6.0
19 75 95 110 2.0
t /t output transition
THL TLH 7 15 19 22 ns 4.5 Figs 6 and 7
time
6 13 16 19 6.0

September 1993 5
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

DC CHARACTERISTICS FOR HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

1An 0.70
2An 0.70
nE 1.35

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tf = tf = 6 ns; CL = 50 pF

Tamb (C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER UNIT V WAVEFORMS
CC
25 40 to 85 40 to 125 (V)
min. typ. max. min. max. min. max.
t /t propagation delay
PHL PLH nAn to Yn 16 34 43 51 ns 4.5 Fig.6
t /t propagation delay
PHL PLH nE to nYn 16 34 43 51 ns 4.5 Fig.7
t /t output transition
THL TLH time 7 15 19 22 ns 4.5 Figs 6 and 7

September 1993 6
Philips Semiconductors Product specification

Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to

VCC.

Fig. Waveforms showing the address input (nAn) to output (nYn) propagation delays
6
transitionand the output
times.

(1) HC : VM = 50%; VI = GND to

VCC.

Fig. Waveforms showing the enable input (nE) to output (nYn) propagation delays
7
transitionand the output
times.

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993 7
 August 1995

1
DM74ALS151
DM74ALS151
1 of 8 Line Data
Selector/Multiplexer

General Description Features

Data
of 8 Line
This Data Selector/Multiplexer contains full on-chip decod- Y Advanced oxide-isolated, ion-implanted Schottky TTL
ing to select one-of-eight data sources as a result of a process
unique three-bit binary code at the Select inputs. Two · Switching performance is guaranteed over full
com-plementary outputs provide both inverting and non- tempera- ture and VCC supply range
inverting buffer operation. A Strobe input is provided · Pin and functional compatible with LS family counter-part
which, when at the high level, disables all data inputs and
forces the Y out-put to the low state and the W output to · Improved output transient handling capability
the high state. The Select input buffers incorporate
internal overlap features to ensure that select input
changes do not cause invalid output transients.

Multiplexer
Selector/
Connection Diagram Function
Table
Dual-In-Line Package
Inputs Outputs
Select Strobe
Y W
C B A S
X X X H L H
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
e e e e
H High Level, L Low Level, X Don’t Care D0 thru D7 the level of the respective D input

TL/F/6203 –
1
Order Number DM74ALS151M or
DM74ALS151N See NS Package Number
M16A or N16A

C
1995 National Semiconductor Corporation TL/F/6203 RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
Supply Voltage 7V Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond
Input Voltage 7V which the safety of the device cannot be guaran-teed. The device
should
definednotin bethe
operated at these limits. The parametric values
Operating Free Air Temperature Range ‘‘Electrical Characteristics’’ table are not
DM74ALS 0§C toa 70§C
guaranteed at the absolute maximum ratings. The
b a
Storage Temperature Range 65§C to 150§C ‘‘Recommended Operating Conditions’’ table will define the
Typical iJA conditions for actual device operation.
N Package 78.0§C/W
M Package 107.0§C/W

Recommended Operating Conditions

Symbol Parameter DM74ALS151 Units
Min Nom Max
V
CC Supply Voltage 4.5 5 5.5 V
V
IH High Level Input Voltage 2 V
V
IL Low Level Input Voltage 0.8 V
I b
2.6
OH High Level Output Current mA
I
OL Low Level Output Current 24 mA
T
A Free Air Operating Temperature 0 70 §C

Electrical Characteristics e e
over recommended operating free-air temperature range. All typical values are measured at VCC 5V, TA 25§C.
Symbol Parameter Conditions Min Typ Max Units
V e eb b
IK Input Clamp Voltage VCC 4.5V, IIN 18 mA 1.5 V
V e e
OH High Level VCC 4.5V, IOH Max 2.4 3.2 V
Output Voltage
eb e b
IOH 400 mA, VCC 4.5V to 5.5V VCC 2 V
V VCC
e
4.5V
OL Low Level 74ALS
e 0.35 0.5 V
Output Voltage IOL 24 mA
e e
II Input Current at VCC 5.5V, VIN 7V
0.1 mA
Max Input
Voltage
I e e
IH High Level Input VCC 5.5V, VIN 2.7V 20 mA
Current
I e e b
IL Low Level Input Current VCC 5.5V, VIN 0.4V 0.1 mA
I e e b b
O Output Drive Current VCC 5.5V, VOUT 2.25V 30 112 mA
I e
CC Supply Current VCC 5.5V
e 7.5 12 mA
All Inputs 4.5V

2
Sw itching Characteristics over recommended operating free air temperature range (Note 1)

Symbol Parameter Conditions From To DM74ALS151 Units

Min Max
t e
PLH Propagation Delay Time VCC 4.5V to 5.5V
e Select Y 4 18 ns
Low to High Level Output CL 50 pF
t e
RL 500X
PHL Propagation Delay Time Select Y 8 24 ns
High to Low Level Output
t
PLH Propagation Delay Time Select W 7 24 ns
Low to High Level Output
t
PHL Propagation Delay Time Select W 7 23 ns
High to Low Level Output
t
PLH Propagation Delay Time Data Y 3 10 ns
Low to High Level Output
t
PHL Propagation Delay Time Data Y 5 15 ns
High to Low Level Output
t
PLH Propagation Delay Time Data W 3 15 ns
Low to High Level Output
t
PHL Propagation Delay Time Data W 4 15 ns
High to Low Level Output
t
PLH Propagation Delay Time Strobe Y 4 18 ns
Low to High Level Output
t
PHL Propagation Delay Time Strobe Y 4 19 ns
High to Low Level Output
t
PLH Propagation Delay Time Strobe W 5 19 ns
Low to High Level Output
t
PHL Propagation Delay Time Strobe W 5 23 ns
High to Low Level Output
: See Section 5 for test waveforms and output load.

Note 1

3
Logic
Diagram

TL/F/6203 –
2

4
Physical Dimensions inches
(millimeters)

S.O. Package (M)

Order Number
DM74ALS151M NS
Package Number M16A

5
 Physical Dimensions inches (millimeters)
(Continued)
DM74ALS151 1 of 8 Line Data
Selector/Multiplexer

Molded Dual-In-Line Package

(N) Order Number
DM74ALS151N NS Package

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices 2. A critical component is any component of
or a life
systems which, (a) are intended for surgical support device or system whose failure to
implant perform can
into the body, or (b) support or sustain life, and be reasonably expected to cause the failure of
whose the life
failure to perform, when properly used in support device or system, or to affect its
to the
accordance safety or
user.with instructions for use provided in the labeling, effectiveness.
can
be reasonably expected to result in a significant
injury

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
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Italiano Tel: (a49) 0-180-534 16 Fax: (852) 2736-9960
National does not assume any sibility for use of any nd National reserves the right at any time to change said circuitry and specifications.
respon circuitr 80 without notice
y described, no circuit patent licenses are
implied a