Engs 31 / CoSc 56

DIGITAL ELECTRONICS
Day 5

Today: Tomorrow:
Minimizing logic (§6.2), Storing Bits Karnaugh Maps

5.1
Housekeeping
Homework 0 due now (bring it up to the front)

Homework 1 posted (Due April 11)

Homework Grading

Lab 1 this week (revised version online now)

Prelab due at beginning of lab
Lab report due at beginning of next week’s lab

Reading quiz for tomorrow (6.2)

Couch Lab tomorrow (Karnaugh maps in small groups)

4.2
 Decoders, Multiplexers, and Encoders, revisited

0
n=0,1,…N–1 1

… N-1

A0
A1 Y
…

AN-1 SEL

n
…

4.3
Some things simplify, others don’t
Why does
X Y X’Y+ X’Y’
X’Y + X’Y’ simplify, 0 0 1
X’Y + X’Y’ = X’(Y+Y’) = 0 1 1
X’ 1 0 0
1 1 0

X Y X’Y+ XY’
0 0 0
but 0 1 1
X’Y + XY’ = X  Y does not 1 0 1
simplify? 1 1 0

5.4
Basic simplification mechanism

X Y X’Y+ X’Y’
0 0 1
Y is both 0 and 1 while X is 0. { 0 1 1
“Logical adjacency” 1 0 0
1 1 0

X Y X’Y+ XY’
0 0 0
0 1 1
Doesn’t happen here { 1 0 1
1 1 0

Simplification happens when one variable (A) changes while the

others (B) stay the same. Then (A+A’)B = B.
5.5
Logical adjacency
Two bit patterns (vectors) X = (x1, x2, x3, … xn) and Y = (y1, y2, y3, …
yn) are logically adjacent if they differ in only one bit.
0 and 1 are logically adjacent
1101 and 1001 are logically adjacent
1101 and 1000 are not logically adjacent
Two rows of a truth table are logically adjacent if their input vectors are
logically adjacent.

The truth set of a logical function is the set of input vectors which
make the function true. A logical function can be simplified if
elements of its truth set are logically adjacent.

5.6
Karnaugh maps: graphical Boolean algebra
Display logical adjacency pictorially.

X´Y + XY = Y

Each cell represents a row of the truth table. Physically adjacent cells
(horizontal or vertical, not diagonal) are logically adjacent.

Map makes simplifications obvious — look for pairs of physically (i.e.,

logically) adjacent cells.

5.7
3-variable Karnaugh maps
Simplifications occur in groups of two or four.

X’Y’Z’ + X’YZ’ + XYZ’ + XY’Z’ X’YZ’ + X’YZ + XYZ’ + XYZ

(X,Y) codes are
ordered so that one
bit changes at a
time; columns are
logically adjacent

5.8
4-variable Karnaugh maps
Simplifications occur in groups of two, four, or eight

5.9
Example: BCD

Let x = 0.
Minimize y0

4.10
More definitions
A minterm is a Boolean expression that covers only one cell of a
Karnaugh map. For example, on a two-variable map,
m0 = X’Y’, m1 = X’Y, m2 = XY’, m3 = XY

Any Boolean function can be written in SOP form as an OR of

minterms:
f = X’Y + XY’ = m1 + m2 = S m(1, 2)

An implicant is a product term (AND) that makes a function true.

In f = XYZ + XYZ’ + X’Y’Z,
XYZ, XYZ’, X’Y’Z are implicants
XY is also an implicant (=XYZ + XYZ’)
X’YZ is not an implicant

5.11
Overlapping coverings are OK
The best coverings use the largest groups.
A prime implicant is a circled group of 1-cells that can’t be made any
larger by circling adjacent cells.

X’Z’ and Y are

prime implicants.
X’Y and XY are not
prime.

5.12
A minimal SOP is a sum of prime implicants

X + Z’

X’Z’ + X’Y + YZ — but do we need

X’Y?

An essential prime implicant covers cells that are covered by no other

prime implicant. Essential prime implicants must be included in any
minimal sum.

5.13
Exclusive-OR patterns
No logical adjacency

5.14
Incompletely specified functions (don’t cares)
Example: Increment a binary-coded decimal (BCD) digit.

Rows 10-15 are

unspecified,
because only 0-
9 occur in BCD.

5.15
Logic minimization using don’t cares

Grouping only the 1’s,

y0 = x3’x0’ + x2’x1’x0’
Five literals, three gates

Including some don’t cares with the 1’s,

y0 = x0’
One literal, no gates

5.16
CAD methods for logic minimization
By-hand Karnaugh minimization is virtually impossible for more than 5 or 6
variables.

Quine-McCluskey algorithm (1956)

Systematically identifies prime implicants and selects the best set.
NP-complete (takes a very long time for large functions).

Espresso algorithm (1984)

Heuristic, achieves a “pretty good” solution in reasonable time.
Exists in some form in all CAD systems.

For details, see Katz, §2.4

5.17
Implementation: programmable logic device (PLD, CPLD)
AND gate inputs
programmed via this Sum of products
connection matrix. with wide OR gate

Ref: Texas Instruments

5.18
Implementation: field programmable gate array (FPGA)
XOR for arithmetic

LUT (lookup table) is Single bit storage (flip

a 4-input logic flop)
function, implemented MUXs route signals: program signal
with memory paths, and combine LUTs into larger Ref: Xilinx
technology, not gates. logic functions.
5.19
Minimizing POS forms
How to convert SOP to POS, algebraically
f(A,B) = AB’ + A’B

Complement both sides, reduce to SOP

f’ (A,B) = ( AB’ + A’B )’ =
(AB’)’ (A’B)’ (DeMorgan)
= (A’ + B) (A + B’) (DeMorgan)
= A’A + A’B’ + BA + BB’ (Distributive)
= A’B’ + AB

Complement both sides again, manipulate into POS

f(A,B) = ( A’B’ + AB )’ = (A’B’)’ (AB)’ (DeMorgan)
= (A+B) (A’+B’) (DeMorgan)

5.20
Karnaugh maps for POS forms
A maxterm is a Boolean expression that covers all but one cell of a
Karnaugh map. For example, on a three-variable map,
M0 = m0’ = (X’Y’Z’)’ = X + Y + Z (using DeMorgan)
M1 = m1’ = (X’Y’Z)’ = X + Y + Z’

Any Boolean function can be written in POS form as an AND of

maxterms

f = S m(1, 2, 3, 4, 7) = (S m(0, 5, 6) )’
= P M(0, 5, 6)
= (X+Y+Z)(X’+Y+Z’)(X’+Y’+Z)

5.21
Example: a 3-variable function from last time
This logical function

Y = (A’ + BC)•(AC’ + B) + AB’

Reduced, after three steps of Boolean algebra, to a sum-of-products

Y = A’B + BC + AB’

And after eight more steps, to a product-of-sums

Y = (A’ + B’ + C) • (A + B)

5.22
Example: On a Karnaugh map
BC
00 01 11 10
A

Sum of products: Group the ones on the Karnaugh map

f = S m(1, 5, 7) = ( literals, gates)

Product of sums: Group the zeros, then take the complement

f ’ = S m(0, 2, 3, 4, 6) =
f = (Z’ + X’Y)’ = ( literals, gates)

Many programmable logic devices can implement either SOP or POS.

CAD software chooses the simpler form.

5.23
Implementing SOP or POS
An XOR gate is a programmable inverter

If P=0, Y=X
If P=1,
Y=X’
If you follow an AND-OR array with a programmable inverter,
you can implement SOP or POS. Some programmable logic
devices have this built-in. Suppose X = AB + C’D
If P=0,
Y = AB + C’D
If P=1,
Y = (A’+B’)(C+D’)

5.24
Alternate 7-segment decoder
Build NOT gates (low true) into truth table

How will you handle 10-15? 4.25

Your designs

g=

5.26
Back to electronics: review propagation delay
Example: 74LS00 Quad 2-input NAND gate

9.5 ns 15 ns
average worst case

6.27
Circuits with feedback
Because of timing delays, feedback can have interesting effects.

Ring oscillator

Even number of inverters?

6.28
Basic two-state circuit
Feedback with NOR gates: Set-Reset (SR) latch

Vahid (first edition)

6.29
Fixing the SR latch
“Enable” input permits latching to be controlled, but S=R=1 ambiguity
remains.

Vahid (first edition)

6.30
Transparent D latch

Forcing S=R’ solves the Transparent (Q follows D)

problem. Resulting device can while C=1, latched when C=0.
latch one bit of information.

Vahid (first edition)

6.31
Edge-triggered D flip-flop
Transparent latch responds to input while clock is high (level-sensitive).

Edge-triggered flip-flop only responds when the clock is changing (typically

rising rather than falling) — much narrower window is an advantage.

Common clock signal synchronizes all the storage elements in a system.

D flip-flop
D latch D latch
D Q’
Dm Qm Ds Qs’

Q
Cm Cs Qs
master servant

Clk

Master-servant design illustrates concept, but is not a good design. See Katz,
§6.1.5, for a better one (and explanation).
Vahid, Fig 3.25
7.32
What can we do with flip-flops?
We can build systems with memory.

Registers (hold numbers for calculations, data to send, data

received…)

Counters (e.g., digital clocks…)

Systems which execute a sequence of operations (these are

called finite-state machines)

6.33