Engs 31 / CoSc 56

DIGITAL ELECTRONICS
Day 4

Today: Monday:
Combinational logic blocks (§§2.7- Logic minimization (§6.2)
2.10)

4.1
Housekeeping
Lab Section assignments:
• 5 sections -> 4 sections (No W 2-5)
• 100% partners in the same section
• 85% of students got their first choice
• 100% of students got their first or second choice
• Let us know ASAP if there was a mistake!

Homework 0 due Monday at 12:30 in class.

Homework 1 will be posted today (due 4/11)
Lab 1 will be posted today. (Prelab due at the beginning of lab)

Crash course feedback

4.2
CMOS Reminder
An MOS transistor is a voltage-controlled resistor.

n-channel (NMOS) transistor — increase Vgs, decrease

Rds (Vgs ≥ 0);
HIGH gate voltage closes switch.
LOW gate voltage opens switch.

p-channel (PMOS) transistor — decrease Vgs, decrease

Rds (Vgs ≤ 0)
HIGH gate voltage opens switch.
LOW gate voltage closes switch.

3.3
More CMOS logic circuits
Identify the functions.

A B Y A B Y
L L L L
L H L H
H L H L
H H H H

3.4
CMOS AND gate
AND is really a “NOT NAND”

NAND NOT

3.5
Efficient implementation of SOP form
Begin with the AND-OR circuit

Put a bubble at each end of the intermediate wires (double negation → no

change in logic)

Recall the two “DeMorgan equivalent” versions of the NAND gate:

We can implement the AND-OR form with NANDs only!

3.6
Exercise: NAND/NOR Implementation
A logic function to be implemented
n X Y Z P
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1

Write a logic equation in simplest form (SOP or POS) and draw the circuit
using only NANDs or NORs.

2.7
n X Y Z P
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1

4.8
 Another interpretation of inverting gates

Separate logic (0, 1) from voltage (high, low).

One way: The bubble indicates a change of logical value from true to
false.

A A’

Another way: The bubble indicates a change of assertion level from

“high true” to “low true”.

A.H A.L A.L A.H

4.9
Why use active-low?
Active-low outputs are better for controlling external devices (e.g., light-
emitting diode) because they can handle more current in the LOW state
than in the HIGH state.

Resistor limits current, protects

LED

Light-emitting diode (LED)

A.H A.L Inverter “sinks” current to light

the LED

Logically, “A=1” turns on the LED. Electrically, a low output turns on the LED.
Separate logic and voltage.
4.10
Connecting voltage with logic — NAND gate
Positive logic interpretation — NAND (NOT AND) function. Bubble
indicates logical inversion.
A.H
(AB)’.H
B.H

Mixed logic interpretations. Bubble indicates voltage inversion

A.H B.H Y.L A.L B.L Y.H

L 0 L 0 H 0 L 1 L 1 H 1
L 0 H 1 H 0 L 1 H 0 H 1
H 1 L 0 H 0 H 0 L 1 H 1
H 1 H 1 L 1 H 0 H 0 L 0

A.H A.L
(AB).L (A+B).H
B.H B.L

The same electronic circuit can implement either an AND gate or an OR gate,
depending on the choice of logic-voltage mapping.
4.11
Connecting voltage with logic — NOR gate
Positive logic interpretation — NOR (NOT OR) function
A.H
(A+B)’.H
B.H

Mixed logic interpretations

A.H B.H Y.L A.L B.L Y.H

L 0 L 0 H 0 L 1 L 1 H 1
L 0 H 1 L 1 L 1 H 0 L 0
H 1 L 0 L 1 H 0 L 1 L 0
H 1 H 1 L 1 H 0 H 0 L 0

4.12
Functional hierarchy
Functional blocks
Design is easier if we can identify
SEL
logical functions that do more than
simple gates.
A0 0
Y
1
A1
Logic gates

Electronics

4.15
Some medium-scale logical functions

0
Decoding — activating one of many outputs n=0,1,…N–1 1

…
Binary code n applied to input makes output n N-1
true, all others false.

A0

Multiplexing — selecting one of many inputs A1 Y

…
Binary code n applied to SEL input makes output SEL
AN-1
Y equal to input An. Very important function!
n

Encoding — generate binary code for active input

n

…
Asserting input n true makes binary code n appear
at output.
4.16
Decoder

With G=1, one of four outputs is asserted

(i.e., TRUE), selected by bits (S1, S0).

With G=0, all four outputs are deasserted

(i.e., FALSE)

G S1 S0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1
1 0 1 0 0 1 0

1 1 0 0 1 0 0
1 1 1 1 0 0 0

4.17
Typical decoder application—microcontroller
A microcontroller turns peripheral devices on and off. It has a limited number
of input/output connections. Giving each device an “address” and using
an external address decoder uses fewer connections on microcontroller.

Address Device 0
decoder

3 Device 1
µC
…

Device 7

4.18
Decoders come packaged in chips (old way)
Common chips: 74LS138 and 139

3 address bits (C,B,A)

8 active-low outputs (i.e., L=1)
Enable logic: G1 • G2A’ • G2B’

Dual 2-4 decoder

2 address bits (B,A) and one enable
input G.L for each decoder.
4 active-low outputs per decoder

5.19
Building big decoders from smaller ones
Bits w2, w3 enable a w0 w0 y0 y0
w1 w1 y1 y1
group of outputs.
y2 y2
En y3 y3
Bits w0, w1 select an
output with the w0 y0 y4
chosen group. w1 y1 y5
y2 y6
w2 w0 y0 y3 y7
En
w3 w1 y1
y2
En En y3 w0 y0 y8
w1 y1 y9
y2 y10
En y3 y11

w0 y0 y12
w1 y1 y13
y2 y14
Ref: Brown & Vranesic En y3 y15 5.20
2-to-1 multiplexer: principle
One of 2 inputs is selected, according to select bit (SEL).
Use decoder to activate one of the AND gates to pass the input.

SEL

A0 0
1
Y =
A1

Actual CMOS multiplexers are built very efficiently, not using AND-OR gates.

4.21
CMOS logic circuits
A MOS transistor is a voltage-controlled resistor.

n-channel (NMOS) transistor — increase Vgs, decrease

Rds (Vgs ≥ 0);
HIGH gate voltage closes switch.
LOW gate voltage opens switch.
For physical reasons (see Engs 32, 60), source terminal
should be lower than drain (toward ground).

p-channel (PMOS) transistor — decrease Vgs, decrease

Rds (Vgs ≤ 0)
HIGH gate voltage opens switch.
LOW gate voltage closes switch.
For physical reasons (see Engs 32, 60), source terminal
should be higher than drain (toward supply voltage)
3.22
Steering Logic — CMOS transmission gate

s
Turn the transistors “sideways”. When ON,

SOURCE DRAIN pMOS will pass a HIGH from source to drain.

x f nMOS will pass a LOW from source to drain.
Together, they make a good logic switch.

SWITCH OFF SWITCH ON

H L L
s s s

H, L No connection L L H H
x f x f x f

L H H
s s s

4.23
Steering Logic — CMOS transmission gate

s
s
SOURCE DRAIN

x f x f

s
s Logic symbol

s= 0
s f
x f=Z
0 Z
s= 1 1 x
x f=x
Truth table
Equivalent circuit Z = “disconnected”

Ref: Brown & Vranesic 4.24

CMOS multiplexer using transmission gates

w0 w0

s f s

w1 w1 f

Sum-of-products circuit Circuit with transmission gates

(14 transistors) (6 transistors)

Ref: Brown & Vranesic 4.25

CMOS XOR gate using transmission gates
Uses 8 transistors, vs 14 for logic gate implementation

x1
x2

f = x1  x2

Ref: Brown & Vranesic 4.26

Typical multiplexer application
Arithmetic unit in a computer

A0 A1 B0 B1

Sa MUX MUX Sb Multiple input sources

A B
Adder
Sum

Ref: Katz, Fig 4.26

4.27
4-to-1 multiplexer
Use 2-to-4 decoder + four AND gates

SEL0
SEL1
A0 00
A1
A2
01 Y =
10
A3 11

But you can also build a 4-to-1 mux (or larger) from 2-to-1 muxes, and exploit
the efficiency of the 2-to-1 circuit.
4.28
Another way to build a 4-to-1 multiplexer
Made from 2-to-1 multiplexers.
s1 A 2-to-1 MUX can be built using only six
s0 MOS transistors.

Allows highly compact multiplexers to be

w0 0 constructed on a chip.
w1 1
2-level SOP version: 36 transistors
0
f Compact version: 18 transistors
1
These compact MUXes can also efficiently
w2 0 implement arbitrary logic functions (used in
w3 1 some PLDs instead of AND-OR arrays).

Generalizes to arbitrary 2N-to-1 multiplexers.

Ref: Brown & Vranesic

5.29
Common MSI multiplexer chips (old way)

Quad 2-input MUX 8-input MUX

4 bits in parallel
(C,B,A) = select inputs 0-7
SEL = select inputs 0 or 1
/EN = enable W, Y
/EN = low to enable chip
(Q=0 if /EN = high) W = /Y

Dual 4-input MUX

(S1, S0) = select inputs 0-3

/GA = enable YA
/GB = enable YB

5.30
Memory
An array of 2n × m bits.

Input bits An-1..A0 are called “address”

A0
D0
Output bits Dm-1..D0 are called “data”

One m-bit data vector is stored at each

…
address.
Dm-1

…
Applying address causes corresponding An-1
data vector to appear at output.

4.32
Memory block can implement combinational logic

F0 = A' B' C + A B' C' + A B' C

MEMORY
F1 = A' B' C + A' B C' + A B C 8 words by
ｴ
4 bits

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C' A B C F0 F1 F2 F3

address outputs

Source: Katz

Also called a lookup table (LUT) — an alternative to the AND-OR array.

4.33
Lookup tables
Store truth table in memory; no gate circuits.

Vahid, Figure 7.18

5.34
Lookup tables
Suppose a LUT is programmed with (0, 1, 0, 0, 1, 1, 0, 0); what is
the logic function it implements?

Truth table is:

xyz F
000 0
001 1
F=
010 0
011 0
100 1
101 1
110 0
111 0

5.35
Encoders
An encoder converts input into more compact (encoded) form.

w0
y0
2n n
inputs outputs
yn – 1
w2n – 1

Opposite of decoder.
w0 y0
n
inputs 2n
wn – 1 outputs
y2n – 1
Enable En Ref: Brown & Vranesic

5.37
Priority encoders
If more than one input to an encoder is asserted, what should the
output be?
One solution: Prioritize the inputs.

w3 w 2 w 1 w0 y 1 y0 z

0 0 0 0 d d 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

Index of asserted input with highest priority.

z=0 if no inputs are active.

Ref: Brown & Vranesic

5.38
Typical priority encoder application
Microcomputer responding to “interrupts” from peripheral devices. If
more than one device requests service, microcontroller knows
which one to serve, based on priority.

Device 0
Priority
encoder
µC
Device 1 3

Device 7

5.39
Summary
s0
s1

A0 00
A1 01 f

Multiplexing — selecting one of many inputs A2

A3
10
11

w0 y0
n
2n
Decoding — activating one of many outputs inputs
wn-1
outputs

Enable En y2n-1

ROM
8 words by
ｴ
Memory — implement logic as lookup tables 4 bits

A B C F0 F1 F2 F3
address outputs

4.40
Review: Half adder
Wires carry logical values (0, 1) or voltages (low, high).

AB’

A⊕B

A’B

AB

But recall that a half-adder cannot handle a carry-in.

2.41
Full adder
Add multi-bit binary numbers
Carry out Carry in

1 1
111
+ 011
101 0

Sum bit
The basic column operation has three inputs and two outputs.
CARRY IN
CARRY OUT
FULL
ADDEND X
ADDER
SUM
ADDEND Y

4.42
Design example: Full adder

Cin X Y Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic equations

4.43
Simplified full adder
The sum function can be rewritten in terms of XOR:

The carry function can be simplified:

Algebraic manipulations also get us here, but there is a better way.

4.45