Engs 31 / CoSc 56

DIGITAL ELECTRONICS
Day 3

Today: Wednesday:
Basic electronics, logic circuits Combinational logic blocks
(§§2.1-2.3, 2.8) (§§2.7-2.10)

3.1
DeMorgan’s laws
Y = AB: Both A and B must be true to make Y true.
 Either A or B can be false to make Y false: ( AB )’ = A’ + B’

Augustus DeMorgan
(1806-1871)

Y = A+B: Either A or B true will make Y true.

 Both A and B must be false to make Y false: ( A + B )’ = A’ B’

Generalizes to multiple variables.

( X1 X2 … Xn )’ = X1’ + X2’ + … + Xn’
( X1 + X2 + … + Xn )’ = X1’ X2’ … Xn’

2.2
Proof of DeMorgan’s Law (2 Variables)

A B AB (AB)’ A’ B’ A’+B’
0 0
0 1
1 0
1 1

A B A+B (A+B)’ A’ B’ A’B’

0 0
0 1
1 0
1 1

3.3
Measures of logical complexity
Literals: gate inputs, wires

Gates: space on chip

Packages: space on circuit board

Speed: each gate has a finite propagation delay from input to

output.

Optimizing size and speed is a goal of logic design.

Boolean algebra can help us accomplish this goal.

2.4
Example
We want to implement this logical function

Y = (A’ + BC)•(AC’ + B) + AB’

First, “multiply out” the ANDs with the distributive axiom:

Y = A’AC’ + A’B + ABCC’ + BBC + AB’

Then, use the facts XX’ = 0 and XX = X:

Y = 0•C’ + A’B + AB•0 + B•C + AB’

Finally, we know that 0•X = 0:

Y = A’B + BC + AB’

2.5
Example (2)
Sometimes DeMorgan’s law allows further simplification:

Y = A’B + BC + AB’

Y’ = (A + B’) • (B’ + C’) • (A’ + B) DeMorgan

= (AA’ + AB + A’B’ + B’B) • (B’ + C’) multiply out
= (AB + A’B’) • (B’ + C’) XX’ = 0
= ABB’ + ABC’ + A’B’B’ + A’B’C’ multiply out
= ABC’ + A’B’ + A’B’C’ XX’ = 0, XX = X
= ABC’ + A’ B’ X+1 = 1, X•1 = X

Y = (A’ + B’ + C) • (A + B) DeMorgan again

2.6
Example (3) — Implementation

(A’ + BC)•(AC’ + B) +
AB’
7 gates, 8 literals, 4 levels

AB’ + A’B + BC (A+B) (A’ + B’ + C)

4 gates, 6 literals, 2 levels 3 gates, 5 literals, 2 levels

2.7
Canonical forms for logic expressions
Sum-of-products (SOP) — also called disjunctive normal form

f(A,B) = AB’ + A’B

Product-of-sums (POS) — also called conjunctive normal form

f(A,B) = (A’+B’)(A+B)

Advantages of expressing logic functions in canonical forms:

• Canonical forms are only two-levels deep, so they have lowest
propagation delay.

• Canonical forms enable simple programmable structures.

SOP form is easier to derive than POS form.

2.8
Example — PAL16L8 programmable SOP array
16 input/output pins, 8 AND-OR functions (half shown here)

Ref: Texas Instruments

2.9
Design flow (so far)
Whether by truth table or other means, derive a logic equation.

Simplify the logic equation to a sum of products form with as few terms
as possible.

Implement with discrete gates or programmable logic.

Good news: We have better methods for simplifying logic than

algebraic manipulation!

2.10
Exercise
A logic function to be implemented
n X Y Z P
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1

Write a logic equation in simplest form (SOP or POS)

2.11
Canonical forms for logic expressions
Sum-of-products (SOP) — also called disjunctive normal form

f(A,B) = AB’ + A’B

Product-of-sums (POS) — also called conjunctive normal form

f(A,B) = (A’+B’)(A+B)

Advantages of expressing logic functions in canonical forms:

• Canonical forms are only two-levels deep, so they have lowest
propagation delay.

• Canonical forms enable simple programmable structures.

SOP form is easier to derive than POS form.

How are these functions built, physically?

3.12
Basic electronics
Fundamental quantities
Current — the flow of electric charge
“positive current convention” — we imagine that current is the
flow of positive, not negative, charge.
Amperes (milliamps, mA; microamps, µA)

Voltage — analogous to pressure, causes current to flow

By convention, current flows from positive to negative
(“downhill”)
I
Volts (millivolts, mV; microvolts, µV)

I
3.13
Switching theory (1938)
Combinations of switches can be described
by Boolean algebra.
A=TRUE closes switch

A+B Claude Shannon

(1916-2001)

A=FALSE closes switch

A•B A´

3.15
Relay logic
A relay is an electrically-controlled switch.

When current flows through the

relay coil, the contacts close and
current flows to the lamp.

NOT function
When current flows through the
relay coil, the contacts open and
the current ceases to flow to the
lamp.

3.16
Relay logic

AND function

OR function

f(A,B) = ?

3.17
First binary adder (1937)
Built at Bell Telephone
Laboratories, from surplus
telephone relays.

Its successors, the “Bell Relay

Computers”, were used
extensively during World War
II.

First use of remote job entry

(computing over phone lines),
Dartmouth to New York
(1940).
George Stibitz (1904-1995)
Member of Dartmouth faculty, 1965-1983

3.18
The first computer bug (1945)

Page from Grace Hopper’s notebook.

Rear Admiral Grace Hopper (1906-1993), USS Grace Hopper

creator of the first compiler.
3.20
Electronic logic gates
Electromechanical (relay) logic replaced by vacuum-tube circuits
(1943–1959), discrete transistor circuits (1959-1964), and
integrated circuits (1964-present).

Dual core processor

(more than a billion transistors)

Source: Vahid, Digital Design (Wiley, 2006), Fig 2.3(a)

3.21
More basic electronics
All materials (except superconductors) resist the flow of current.
Resistance measured in ohms (W).

Ohm’s Law: V = I R (volts = amps • ohms)

How much voltage (pressure) V is required I

to produce current (flow) I against a
resistance R? V = IR V R
What is the current I through a resistance
R produced by a voltage V? I = V/R

What is the drop in voltage V caused by a

flow of current I through a resistance R? I R V
V = IR

3.23
Power dissipation in electronics

Current flowing through

resistance causes power to be
dissipated as heat:

P = I2R

Design goal: minimize current,

minimize resistance

http://xkcd.com/643/

3.24
How a transistor works
An MOS transistor is a voltage-controlled resistor.

Source: Vahid, Digital Design (Wiley, 2006), Fig 2.4

3.25
CMOS logic circuits
An MOS transistor is a voltage-controlled resistor.

n-channel (NMOS) transistor — increase Vgs, decrease

Rds (Vgs ≥ 0);
HIGH gate voltage closes switch.
LOW gate voltage opens switch.

p-channel (PMOS) transistor — decrease Vgs, decrease

Rds (Vgs ≤ 0)
HIGH gate voltage opens switch.
LOW gate voltage closes switch.

3.26
Complementary MOS (CMOS) inverter

If Vin is HIGH
s
g Upper (PMOS) transistor is off, lower
“pull-up”
(NMOS) transistor is on  Vout is LOW
d

d
g
“pull-down” If Vin is LOW
s
Upper transistor on, lower transistor off 
Vout is HIGH

Almost no current flows in either state, but as

transistors get smaller, more current leaks through the
“off” switch, wasting power.

3.28
 Representing ‘1’s and ‘0’s by voltages
Bad idea: vulnerable to noise

VDD (5V, 3.3V)

‘1’

VDD/2

‘0’

0V

Ref: Prof K. Odame, Engs 32 3.29

 Noise robustness

• Say G1 outputs a ‘0’

• G1 output corrupted ‘1’ ‘1’

by noise

• G2 may read it as a ‘1’

‘0’ ‘0’

G1 G2

Ref: Prof K. Odame, Engs 32 3.30

 Representing ‘1’s and ‘0’s
Better idea: different acceptable ranges for input and output
VDD VDD
‘1’
VOH

‘1’

VIH
Invalid range
VIL

‘0’
VOL
‘0’
0V 0V

OUTPUT ranges INPUT ranges

Ref: Prof K. Odame, Engs 32 3.31

 Noise robustness

• Say G1 outputs a ‘0’ ‘1’

• G1 output corrupted ‘1’

by noise

• G2 still reads it
as a ‘0’

‘0’

‘0’
G1 G2

Ref: Prof K. Odame, Engs 32 3.32

 Noise robustness

VDD VDD
‘1’
VOH

‘1’
Noise margin

VIH
VIL

Noise margin
‘0’
VOL
‘0’
0V 0V

Consult data sheet for values of VOH, VOL, VIH, VIL.

Ref: Prof K. Odame, Engs 32 3.33
 Output current drive

Output current depends on state of transistors, e.g., set Vin= 0 V

VDD

Iout
Vin = 0V Some other circuit (load)

+
Vout

Ref: Prof K. Odame, Engs 32 3.34

 Output high current drive
Upper (pMOS) transistor sources current when output is high.

Current is limited by pMOS transistor’s channel resistance,

IOH = (VDD – VOH)/RONp

VDD

RONp

IOH
Vin = 0V Some other circuit

+
Vout = VOH

-
Ref: Prof K. Odame, Engs 32 3.35
 Output low current drive
Lower (nMOS) transistor sinks current when output is low.

Current is limited by nMOS channel resistance,

IOL = VOL/RONn
VDD
Consult data sheet for
values of IOH, IOL.

IOL
Vin = VDD Some other circuit

+
RONn
Vout = VOL

Ref: Prof K. Odame, Engs 32 3.36

More electronics — capacitance
The ability of a material to store charge is called capacitance.

Basic physics: Charge (Q) = Capacitance (C)  Voltage (V)

Because of capacitance, voltage cannot change instantaneously:

Rate of voltage change = Rate of change of stored charge 
1/C
= Current / Capacitance
An instantaneous voltage change would require an infinite current.

6.37
More electronics — capacitance
Charging a capacitor — basic RC circuit

6.38
Capacitance causes propagation delay

One CMOS circuit driving another

CMOS circuit

Equivalent circuit:
First circuit’s transistor outputs act like
resistors to +5 V and ground.

Second circuit’s inputs act like

capacitors, charged by the first circuit.

The first circuit isn’t switched until its

output rises to VOH or falls to VOL,
governed by the RC charging.

6.39
Power consumption

Transistors are “leaky”: small amounts of current are always flowing to ground,
dissipating heat in resistance ⇒ static power

It takes energy to charge or discharge a capacitor: CV2/2 (joules) every time a circuit
switches. If a circuit cycles low-high-low every T (seconds), then energy is used at a
rate CV2/T = fCV2 (watts) ⇒ dynamic power

Dynamic power is proportional to cycle

frequency (f). To reduce dynamic power
without sacrificing speed, make
transistors smaller (less C), and reduce
supply voltage (V).

6.40
 Propagation delay
Gate inputs (pMOS and nMOS transistors) have parasitic capacitance, which
must be charged by the driving circuit.
Vout reaches its final value when load capacitances are charged ⟹ propagation
delay.
The more loads (fanout), the more capacitance, the higher the delay.
Consult data sheet for values of propagation delay, tPLH, tPHL

Vin Vout

Ref: Prof K. Odame, Engs 32 3.42

How to read a data sheet (Part 1)
Prefix
SN — Manufacturer code
54 — Military grade
74 — Commercial grade
Technology type
[blank] — plain TTL
L, H — low-power, high
speed (obsolete)
S, LS — Schottky, low-
power Schottky
AS, ALS, F — Advanced
Schottky, Advanced low-
power Schottky, “FAST”
(Fairchild AS)
Pinout — how to wire it up HC, HCT, AHCT — CMOS;
Functional pins HCT & AHCT are TTL-
compatible
Power and ground pins
Logical function
08 = Quad 2-input AND
A, B, etc — suffix indicates
design revisions
Suffix
J, N, D, etc, indicate
packaging, speed, other2.43
attributes
How to read a data sheet (Part 2)

2.44
How to read a data sheet (Part 3)

2.45
More CMOS logic circuits
Identify the functions.

A B Y A B Y
L L L L
L H L H
H L H L
H H H H

3.46
CMOS AND gate
AND is really a “NOT NAND”

NAND NOT

3.47
Efficient implementation of SOP form
Begin with the AND-OR circuit

Put a bubble at each end of the intermediate wires (double negation → no

change in logic)

Recall the two “DeMorgan equivalent” versions of the NAND gate:

We can implement the AND-OR form with NANDs only!

3.48
Efficient implementation of SOP form (2)
Using NANDs (4 transistors) instead of ANDs and ORs (6 transistors)
saves space and time:

Size comparison:
AND-OR: 18 transistors

NAND: 12 transistors

Speed comparison:
AND-OR: 4 levels (NAND-
NOT-NOR-NOT)

NAND: 2 levels

3.49
 Moore’s Law (1965)—more transistors per chip

Andy Grove, Bob Noyce, & Gordon Moore’s graph: number of

Moore, founders of Intel, ca. 1970s transistors on a chip doubles every
year
http://www.businessweek.com/1997/34/b3541106.htm
Source: Electronics, April 19, 1965
3.50
Intel’s “tick-tock” model
Two-year cycle, (1) process technology, (2) architecture

How big is a silicon atom?

Can Moore’s Law continue much longer?
http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html

3.53
Moore’s Law: Transistors keep getting smaller
http://www.intel.com/technology/mooreslaw/index.htm?iid=tech_as+rhc_moore
Wavelength of red (laser pointer) light is
635 nm.

22 nm Intel 4th generation (Haswell) Core

processors (2014).

14 nm Intel (Broadwell, Skylake)

processors (now), working on 10 nm.

Xilinx’ 7-series FPGAs use 28 nm

technology, designing for 20 nm.

Below 10 nm, quantum mechanics takes

over — what will happen to Moore’s
Law?

For (lots) more information, see:

http://www.intel.com/content/www/us/en/silicon-innovations/silicon-technologies-general.html

3.54
Summary

Bits are manipulated by logical AND, OR, and NOT operations, and
more complex operations built from AND, OR, and NOT.

Logical values (1=True, 0=False) are represented physically by High

and Low voltages.

Logical operations are implemented physically by electronic gate

circuits.

There is a trend toward lower supply voltages and narrower noise

margins (we will use 5V and 3.3V supplies in Engs 31).

Engs 31 concentrates on logical functionality. For more details of the

electronic devices and circuits, take Engs 32, 60, 61.

3.57