5-2

Sequenr
~L~og~1~·c~De~s~i~g~n---- -------------------------....: ,a, CirclJlf_
·~.,
Jj ■ Introduction
n)T applications in v.,,hich digital outputs are required to be
There arc n1 a . gener
vith t11c sequence in which the input signals are received. This atec1 i...
accordance ' . . . . reqlli ..,
b e ~atisficd using a combinational logic system. These applicatt ons ren,Pi-,
canno t - -•q
outputs to f"e generated that are not only depend~nt on the present_ input conditi~eqllire
thcv also depend upon the past history of these inputs. The past history is p ns htit
.I rovid
feedback from the output back to the input. ecf by

Fig. 5.1.1 shows the : . --.. -... --. -. --•--· · · •-•••-••-•• ••• • ••--• -••• •--· · -· •..... .
block diagram of sequential ; ...
•. ··

circuit/Finite State Machine : lnputs

Combinational
circuit
...
-
(FSM). As shown in the . (Combinational
component)
Fig. 5.1.1, memory elements
.
'
'
j
Memory

-
are connected to the '
'
' elements
'
combinational circuit as a '
'
' Present state (Sequential Nextstate
'
feedback path. '
'
component)
'
'
. . . . ........
'
The information stored ,_ ------ -... - ... -- - -- - ---- ---- -. ----... ---- ......... ---.. --- - -- - -- - -. ---.
in the memory elements at Sequential circuit
any given time defines the Fig. 5.1.1 Block diagram of sequential circuit / FSM
present state of the
sequential circuit. The present state and the external inputs determine the outputs and
the next state of the sequential circuit. Thus we can specify the sequential circuit by a
time sequence of external inputs, internal states (present states and next states), and
outputs. The counters and registers are the common examples of sequential circuits.

The memory element used in sequential circuits is a flip-flop which is capable of storing 1-bit
binary information.

1--111 Comparison between Combinational and Sequential Logic Circuits

Sr. Combinational circuits Sequential circuits

No.
1.
-------------
In combinational circuits, the output In sequential circuits, the output variableS
variables are at all times dependent on the depend not only on the present inpd
combination of input variables. variables but they also depend uPon the
past history of these in~t variables.
2. Memory unit is not required in Memory unit is required to store the~
combinational circuits. history of input variables in the sequ
circuit.

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cornbinational circuits are faster in speed

t,ecause the delay ~etween input and output
is due to pro agation dela of ates.
5-3 Sequential Circuits - I

Sequential circuits are slow er than

combinational circuits.
the .

Combinational circuits are easy to design.

' Seque~tial circuits are comparatively hard
to design. er
parallel adder is a combinational circuit. Se • 1 dd .
. na a er is a sequential circuit.
Table 5.1.1 Comparison between combination d
aI an sequential circuits
dfl Clock
A clock signal is a particula r type of signal ~ ;~~~~ ~
that oscillates between a high and a low state
and is utilized to co-ordin ate actions of
circuits. It is produce d by a clock generator. Fig. 5.1.2 Clock signal
The most common clock signal is in the form
of a sq~are _wave with . a 5?
% ~uty cycle, usually with a fixed, constant frequency as
shown m Fig. 5.1.2. Crrcuits usmg the clock signal for synchronization may become
active at either the rising edge, falling edge or in the case of double data rate, both in
the rising and in the falling edges of the clock cycle.
The time required to complet e one cycle is called 'clock period' or 'clock cycle'.
Ideally, the clock signal should have sharp transitions from one level to other as shown
in Fig. 5.1.2.

1111 Comparison between Synchronous and Asynchronous Sequential

Circuits

We have already introduc ed to synchron ous sequential circuits. These circuits are
further classified dependi ng on the timing of their signals : Synchronous sequential
circuits and asynchronous sequent ial circuits. In synchronous sequential circuits, signals
can affect the memory element s only at discrete instants of time. In asynchronous
sequential circuits change in input signals can affect memory element at any instant of
time.

Sr. No. Synchro nous sequenti al circuits Asynchronous sequential

circuits
r--.....:__ _:__ :._- ---- --+ ---- ---- ---- -.
1. In synchron ous circuits, memory elements In asynchronous circuits, memory
are clocked flip-flops. elements are either unclocked flip-flops or
--:---._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _:"_time del~ elen1ents.
2. In synchronous circuits, the change in In asynchronous circuits change in input
input signals can affect memory element signals can affect memory element at any
upon activation of clock sigfl:al. instant of time.

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 Because of absence of clock, asynchronoUa
3. . um opcralm
The maxim . g 5tJccd of clock
r circuits can operate faster than
depend s on time delays involved.
5 ~,chron ous circuits .

More difficult to design.

4. Easier to design. • · •
Table 5.1.2 Compa rison betwee n synchronous and asynch ronous sequen tial circuits

m The Basic Bistable Element

The Fig. 5.2.1 shows the basic bistable element used in latche s and flip-flops 'l"1...
· . • ine
basic bistab le eleme nt has two output s Q and Q · It h a s two cross- couple. d inverters •
, I.e.,
•
the outpu t of the first inverte r is connec ted as an mpu t to the second inverte r and th
. e
outpu t of second invert er is connec ted as an input to the firS t invert er.

A--- ~-a A---- 1

I
...
(

8----,- -6
✓ -L;;;,,;;,--...... s-- n--Q 9-e--e
B
(a) Using basic inverter (b) Using NANO gates (c) Using NOR gates
Fig. 5.2.1 Basic bistabl e elemen t (1-bit memor y cell)

The basic bistab le eleme nt circuit has two stable states logic O and logic
1, hence the
name 'bistable'. To illustr ate this, assUµ1e A = 0. "W:b-en A = 0,-...the outpu
t of inverter 1 is
1 (A), i.e., Q = 1. Since the outpu t of inverte r 1 is the input to the invert
er 2, A = B = 1.
Conse quentl y, the outpu t of invert er 2, i.e., B is 0. Since the outpu t of
the inverter 2·is
conne cted to the input of the invert er _2, Q .; B_- A = 9. We have assi
d same value
for A. Thus, the circuit is stable with Q = A = B = 0 and,.Q = A = B
,, = 1 ,U~ing similar
explan ation it is easy to show that if it is assumed- that A = 1, the basic
bistab le element
is stable with Q = A = B = 1 and Q = A = B = 0. This is a secon d
stable condition of
the basic bistab le elemen t.·
The two stable states of basic bistab le eleme nts are used to store two binary
eleme~,
0 and 1. In positiv e logic system , state,Q = 1 is used to store logic 1,
and state Q ; 0 is
used to store logic O_:_ It is impor tant to r:_ote~at the ~o outpu ts ~re
compl,mentary,
That is when Q = 0~ Q = 1; and when_ Q = 1, Q = O. ~ f

From the above discus sion we --can note follow ing things about the
basic bistable
eleme nt.
l. The outpu ts Q and Q arc alway s compl ement ary.
2. The circuit has two stable states. Jbe. state corres ponds to Q =
1 is referred to as
1 state or set state and state corres ponds to Q _ o is referr ed· to
as O'state or
Reset state. • "
-
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\
 jC [)8Sign
~
5- 5 sequential C i ~
If the circu is in the s
3. . the resetit (0) state _et (~) state, it wi ll rem . th •rc ui t is
1!l th t .t ' it ain in the se t sta te an d if
W ill rem ain in the res et state. Th is pr op er ty of e Cl . ui t
ca n store l-b it of digital
shows a 1
_ t-bit me mo ry ce11• information. Th ere foT e th th e cir c
e cir cu it is ca lle d a
'1"'1 •
4 J.1•..e 1-bit in fo rm ati on stor ed ;...,.
,•.u th e c;9
• n,erefore, this cir cu it is ~"cw·t 1·s loc ke d
also referred to as a latch or l atchea \n th e cu • cw·t•
.
eJ Latches
Fe b.- 07 ,08 .
,Ju n"- 10 . l)p< " -\() _\
1.,atcheS an d ~p -~ op ~ bo \
th ar e b_istable ele me nts
t sequential cir cw ts. . Th es e ar e th e ba sic bu ild in
of 11'\0S Th e m am difference be g b\oc'ks
thod used for ch an ~g . .
• th tw ee n lat ch es an d flip-flops
err state. W e us e th e na is in the
tile t normally sa mp les m e flip-flop for a se qu en
its m pu ts an d ch an ge s tia l device
tha()Ckirtg signal. ~ th e oth its ou tp ut s on ly at tim
e~ ha nd , we us e th e n~ es de ter mi ne d by
!eeks all of its in pu t~ co e lat ch for a se q~ en tia
n~ uo us ly and_ ch an ge l device th at
. dent of a clocking sig na s its ~u tp u~ acco~dmg
l. M an y tim es en ab le sig ly at an y tim e
md
Whepe en nenable signal is
. •
ac tiv e outpu t chan ge s
na l 1s pr ov id ed wi th th e latch.
.
. al is not activated in pu t oc cu r as in pu t changes. Bu t wh en
sign ch an ge s do no t affect ou en ab le
tp ut .
- SR Latch
s (Set) A
Fig. 5.3.l sh ow s SR lat
ch wh ic h is 1- bi t
memory cell. As sh ow n in
th e Fig. 5.3.1, tw o
inverters 3 and 4 ar e co nn
ec ted to en te r th e
digital information. In pu t
fo r ga te 3 is S an d R
input for gate 4 is R. Th is (Reset) B
la tc h is als o ca lle d o- --- -o a
RS latch.
Fig. 5.3.1 SR latch
For understanding th e cir
cu it op er at io n, w e m
NAND gate whose on e of us t fir st de te rm in e th
th e in pu t is lo gi c O an e ou tp ut of
output of other NAND ga te d ac co rd in gl y w e ha ve
in th e cr os s co up le d cir to de te rm in e the
gate is 1 if any on e in pu cu it. Be ca us e th e ou tp
t is 0. Th e ci rc ui t op ut of NANO
output of shaded NANO ga er at io n is as fo llo ws . In Fi g. 5.3.2,
te is de te rm in ed fir st, th e
output of shaded NAND as an d th e 0 in pu t th at de cid
1 is sh ow n in bo ld . es th e
Case1: S= R =O •.

In this case, S = R = 1. If
Q is 1, Q an d B in pu ts
an~ hence ou tp ut Q = 0. fo r NA ND gate 2 are bo 1
Si nc e Q th
1, 1.e. Q == l. = 0 an d S = 1, th e ou tp ut
of NAND gate 1 is
If
-QQ - is .0' Q_a nd -R in pu ts
- 1. Smee Q 1 fo r N A N D ga te 2 ar e d h
~
= an d S = 1, th e ou tp ut of N A N 0 an d •1, oan• ence ou tp ut
-
D ga te 1 1s , i.e., Q -- 0•

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 ~~~~~------------3.:~---:::-.-=~-=-~~::---
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·Q
Seq uen tial c·
---- -.:: ~ ~ I
~
Initial state • =1 Q= O ''tt1 it.
'
Init ial stat e : a = O, -a --1

fig . 5.3.2
Th is sho~.,s tha t wh en S = R = uts do not cha n e.
0, the ou
Ca se 2 : S =1and R = O s 0
In this cas e, S = O and R == 1.
Since
S = 0, the out put of NA ND gate 1,
Q = 1 (Recall tha t, for NA ND
any
one or mo re inp ut is O, the out put
is R ___o__ R
l} For NA ND gat e 2, bot h inp uts ,._ _ B 1
Q
and R are 1, thu s out put Q == 0. Fig . 5.3 .3
Th e inp uts S = 1 ~R :-0, ma- - - - - - - - - 7
kes Q = 1, i.e., set sta te.
Ca se 3 : S = O and R = 1 s 0 s 1
In this cas e, S = 1 and R == 0. Sin A
ce
R == 0, the out put of NA ND gat
e 2,
Q = 1. For NA ND gat e 1, bot
h
inp uts Q and S are 1, thu s out
put R __1_ R
Q = 0.
--- B 0
Fig . 5.3 .4
\ Th e inp uts S = 0 and R = 1, ma kes Q = 0, i.e., reset sta
te. \
Ca se 4 : S = 1 and R = 1
Wh en S = R = 1, bo th the ou tpu
ts Q and Q try to bec om e 1 wh
an d the ref ore , this inp ut con dit ion ich is not all -
is pro hib ite d.
SR lat ch us ing NOR gates R (R es et) --'" "" Q
Fig. 5.3.5 sho ws the SR lat ch usi
ng tw o NO R
gat es. As .sh ow n in the Fig. 5.3
.5, the tw o NO R
ga tes are cros~ cou ple d so tha t
the ou tpu t of NO R
ga te 1 is con nec ted to one of
the inp uts of NO R
ga te 2 an d vic e ver sa. Th e lat S (Se t)
ch has tw o ou tpu ts
Q an d Q, an d tw o inp uts , set and
reset. •gN
Fig . 5.3 .5 SR latc h usio
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Logic Design
- 5-7 Sequential Circuits - I

Before going to
. analyse the SR latch we recall that a logic 1 at any input Of a NOR
gate forces 1ts outp t ' . · •t for
. . u to a logic 0. Let us understand the operation of this cirCUl
var.ous input/ output possibilities.
R(Res et)-~
CASE 1 : S = 1 and R = o
In this case, S input of the NOR t 2 . t
. ga e 1s a
logic 1, hence its output, Q is at logic O. Both
inputs to NOR gate 1 are now at logic o. So that
its output, Q is at logic 1. s (Set)

Fig. 5.3.5 (a)

CASE 2 : S = 0 and R = 1 R (Reset )---1

D--+- --Q

In this case, R input of the NOR gate 1 is at

logic 1, hence its output, Q is at logic O. Both
inputs to NOR gate 2 are now at logic 0. So that
its output, Q is at logic 1.
S (Set)
CASE 3 : S = 0 and R = 0
Initially, Q = 1 and Q = 0 'Fig. 5.3.5 (b)

Let us assume that initially Q = 1 and Q = 0 .

With Q = 0, both inputs to NOR gate 1 are at R (Reset)
logic 0. So its output, Q is at logic 1. With Q = 1,
one input of NOR gate 2 is at logic 1, hence its
output, Q is at logic 10. This shows that when S
and R both are low (at logic 0) the output state
does not change. S (Set)
0
Initially, Q = 0 and Q = 1
Fig. 5.3.5 (c)

Let us make opposite assump tion that Q = 0

R{Re set)--
and Q = 1. With Q = 1, one input of NOR gate 1
is at logic 1, hence its output Q is at logic 0.
With Q = 0, both inputs to NOR gate 2 are at
logic 0. So its output Q is at logic 1. In this case
also there is no change in the output state.
S (Set) 1
0
Fig. 5.3.5 (d)

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 Sequential Circuit
a.. I
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CASE 4 : S = 1 and R = 1 tputs of both NOR gates to the

Wh en R and S both are at logic 1, they force the ou . or prohibited state
indeter:rrunate d"ti ' clt\d
low state. (Q = 0 and Q = 0). So "re call this an asterisk (*). This con 1 on ~o Violates
represent this condition in the truth table as an be the complement of Q. ThUs in
the basic definition of a latch that requires ~dtod by making sure fuat l's are I\N
normal operation this condition must b e avo1 e V\

applied to both the inputs simultaneously. h Looking at Fig. 5.3.6

l for SR late • We can
Fig. 5.3.6 shows the symbol and truth tab e
summarize the operation of SR latch as follows: ch e and latch remains latched in.
• With both inputs low, the output does. not at~!ecause nothing changes. 118
last state. This condition is called inactive st
f t h • t ( t
. . th Q output o 1a c 1s se a 1ogic l).
• When R input is low and S input 1s high, e
low, the Q output of latch is reset (at
• When R input is high and S input is
logic 0).
• When R and S inputs both are high, output is unpredictable. This is called
indeterminate condition.

s R a., Qn+1 State

0 0 0 0
0 0 1 1
s Q 0 1 0 0
0 1 1 0
R Q 1 0 0 1
Set
1 0 1 1
1 1 0 X
1 1 1 X

(a) Symbol (b) Truth table

Fig. 5.3.6

I-ffj An Application of the SR Latch : A Switch Debouncer

For interfacing keys to the digital
systems, usually push bottom keys are
V
used. These push button keys when
pressed bounces a few times, closing and o--A 0
opening the contacts before providing a ~B
v-=-
steady reading, as shown in the .I_
V:..1-l--1-11_____[lll[.1
Fig. 5.3.7. Reading taken during
1
bouncing period may be faulty. This
Fig. 5.3.7 Effect of key debOUnGf

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Logic Design
- 5-9 Sequential Circutts - I

Problem is know n as key de b ounce The

s a
Problem of key debounce is und es1rab
:
le
-A---- .--1
and it must be avoided.
One way to avoid key d b v-=-
e ounce
oblem
Pr is to use SR latch Thn . .
• ~ c1rcu1t
used to avoid keybounce with SR latch is
called a switch debouncer. The Fig. _ _
1
537 Fig. 5.3.7 (a) Switch debouncer
shows the switch debou ncer circuit and VA
its waveforms. When key is at positi on
A, the outpu t of SR latch is logic 1, and V - -
when key is at positi on B, the outpu t of t
0
SR latch is logic 0. It is impor tant to VB I
I
note that, when key is in betwe en A and I

B, SR inputs are 00 and hence outpu t

V
I
I
I
I
- - -

7
I

does not change, preve nting debou ncing 0 '--' t

of key output. In other words , we can
(
say that the outpu t does not change
during transition period , elimin ating key
o=+ ---- ---- ---- t
debounce.

Qi-- --

0,-+-_ __.,_ _ _ _ _ _ _ _ t
Jff1 The S R Latch Fig. 5.3.7 (b) Waveforms of switch debouncer

From SR latch using two NOR gates we can const ruct the equiv
alent SR latch using
two NAND gates, as show n in the Fig. 5.3.8.

R (Res et)--.....
D--- +--Q
--- -a

S (Set)
S (Set) --- -a

(a) Basic circuit (b) Replacing NOR gate by bubble d AND gate

Fig. 5.3.8

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.~ ~ o g ~ ic
~D~e~s~
ig ~ n ~ - - - - Sequential Circut
~-----~5_ t
:- ~ 1 0 :_ _ -
- - :: ~ ~ - - - -
--~
R (R e se t) -- .(
". I -R - _ _ ,

S (Set)
o -- -- -- -a D------a
(c) Shifting bu
bb\e
(d) Equivalent N
ANO gate SR la
tc h
3.8 Fig. 5.
Looking at Fig
. 5.3.8, we can
th is la tc h is dif call this latch R
ferent from th s latch or S R
at for th latch. The tr u th
a n d S in p u ts ar e N O R gate latch. It table for
e applied in th is shown in F
ig. 5.3.9. Here,
e complemente R
d form.
s ;
R I 0n Qn+1 State
0 0 0 X
s 0 0 Indeterminate
Q 1 X l
0 1 ' 0
1
R 0 1 1 Set
1
1 0 0 0
1 0 1 Reset
0
1 -
1 0 0
1 1 1 No change(NC)
(a) Lo gi c sy m
1
bo l
table (b) Truth
To understand Fig. 5.3.9
how this circui
low o n any inp t functions, reca
ut to a NAND ll that a
T h u s a low on gate forces its ou
the S input wil tput high.
an d -Q = 0. A lo l set the R Slatc an 0 1
w o n - h, i.e. Q = 1 SR
' - the R input wil .
a n d Q = l. If bo - l reset it, i.e. Q oo o l 1.
th R a n d -S a re = 0 '- ''
in its previou hi gh, the latch w
s state. When b - - ill re m ain 01 0
th e o u tp u t is in oth R and S in
0
valid. pu ts ar e lo w,
11 (x·· X
The functional
behaviour of a
described form latch or flip-flo
ally by a ch p can be
specifies the la aracteristic equa
tch or flip-flop's tion that
it s cu rr en t stat next state as a
e and inputs. fu nction of
Fig. 5.3.10
Look in g at the truth table fo
ch r SR latch and
le aracteristic equation for SR
1...
g et t.1 simplifying Q n+ • b K-map w
1 functio n Y e
latch as Q n+
Fig. 5.3.10. 1 = S+RQ n. 1s 1• 1·uustrate d U. \
- T h'
s

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18■ The follow·
mg waveforms • the
.
Q waveform. Assume initially Q == l. are applied to tl,e inputs oif SR latch. Determine
.
1

R ~
1
s ofl_
a 1•
7
'
r7
al
L,

J l
Fig. 5.3.11

Solution: This example shows that the latch input has to be pulsed momentarily to
• cause a change in the latch output state, and the output will remain in that new state
after the input pulse is over.
even
- The Gated SR Latch
In the SR latch we have seen that
output changes occur ~ediate ly after EN :
s R Qn Qn+t State
I I I
the input changes occur 1.e. the latch is 1 0
I
0
'
0 0 No Change (NC)
sensitive to its S and R inputs at all 1 0 I
0 1 I
1
I

times. However, it can easily be 1 0 1 0 0 Reset

modified to create a latch that is 1 0 1 1 0 '
I
sensitive to these inputs only when an 1 1 0 0 1 Set
enable input is active. Such a latch with 1 1 I
0 1 1
' J

enable input is known as gated SR 1 1 1 0 X Indeterminate

latch. It is as shown in the Fig. 5.3.12. 1 1 ..
1 1 X
The Table 5.3.l shows the truth table 0 X X 0 0 No Change (NC)
for gated latch. As shown by truth 0 X X 1 1
'

table, the circuit behaves like a SR latch Table 5.3.1 Truth table for SR latch with enable
when EN = 1, and retains its previous input
state when EN = 0.
s
s Q
EN EN
R Q

R
(a) SR latch with enable input using NANO gates (b) Logic symbol
Fig. 5.3.12

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