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For The RTL Schematic Provided, Perform Timing Analysis Using The Following Parameters

The document outlines a homework assignment involving timing analysis of an RTL schematic, system design for continuous operation with a specific algorithm, and the creation of state machines and data paths for various coding scenarios. It includes tasks such as identifying critical paths, checking for hold violations, and designing lookup tables based on a given sequence. The assignment requires drawing high-level state machines, data paths, and control unit connections for multiple questions.

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2 views8 pages

For The RTL Schematic Provided, Perform Timing Analysis Using The Following Parameters

The document outlines a homework assignment involving timing analysis of an RTL schematic, system design for continuous operation with a specific algorithm, and the creation of state machines and data paths for various coding scenarios. It includes tasks such as identifying critical paths, checking for hold violations, and designing lookup tables based on a given sequence. The assignment requires drawing high-level state machines, data paths, and control unit connections for multiple questions.

Uploaded by

VĨ VÕ TRẦN GIA
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 8

HW 6

Q1 For the RTL schematic provided, perform timing analysis using the following
parameters :

Propagation Delay Contamination Delay


Register / Flip-flop Parameter Value Component (t_pd) (t_cd)
Clock-to-Q Propagation Delay (t_pcq) 60 ps NOT Gate 10 ps 5 ps
Clock-to-Q Contamination Delay (t_ccq) 25 ps OR Gate 20 ps 10 ps
Setup Time Requirement (t_setup) 15 ps Adder to SUM 40ps 30ps
Hold Time Requirement (t_hold) 85 ps Adder to Cout 18 ps 8 ps
Buffer 8ps 8ps

Note: The adder has two outputs: SUM and Cout. The propagation delay/ contamination delay
for them is different.
(a)​ Mark the critical path in the schematic. What is the highest clock frequency it can run at
without setup time violations? Assume there is no clock skew.

(b)​ Are there any hold violations in the circuit? If any, show in the figure below how you
would fix any hold violations. You should try to maintain the clock frequency as high as
possible. What is the highest clock frequency after the fixing? Assume there is no clock
skew.
Q2 ​ ​ ​

Design a system following the description below to be able to operate continuously—that is,
once a computation is complete, it should be ready to accept a new input. Assume that the
system’s initial state is the IDLE state and the initial INPUT_NUMBER is 0.

Input:

●​ INPUT_NUMBER: A 32-bit number.

Output:

●​ OUTPUT_NUMBER: A 32-bit number.

System Operation:

●​ The system starts in the IDLE state and waits for a new INPUT_NUMBER.
●​ Once an input is received, the system initiates the algorithm described below.

Algorithm Description:

1.​ Initial Approximation:


○​ Right-Shift Operation: Right shift the INPUT_NUMBER by 1 bit.
○​ Subtraction: Subtract the right-shifted value from the constant 0x5F375A86. (In
your RTL design, mark the arithmetic units used in this step as unsigned integer
arithmetic units)
○​ Store Result: Save this result in a register as Y.
2.​ Iterative Calculation:
○​ Floating-Point Calculation: Compute the value using the formula:​
Y1 = Y × (1.5f – 0.5f × INPUT_NUMBER × Y × Y). The INPUT_NUMBER and Y
in this equation are treated as IEEE754 floating-point numbers. (In your RTL
design, mark the arithmetic units used in this step as floating point units)
○​ Convergence Check: Evaluate whether the absolute difference abs(Y1 – Y)
is less than a predefined THRESHOLD. (In your RTL design, mark the arithmetic
units used in this step as floating point units)
■​ If yes: Transition to the IDLE state (output the result).
■​ If no: Update Y with Y1 and repeat the iterative calculation.
3.​ Continuous Operation:
○​ The system must handle continuous operations, being ready to accept a new
INPUT_NUMBER after completing a calculation.

​
(a) Draw a minimum state HLSM to represent the above system.

​
​ ​ ​ ​ ​ ​ ​ ​

(b) Draw the circuit representing the data-path of this system. Use RTL design. ​ ​

​ ​ ​ ​ ​ ​ ​ ​ ​

(c) Draw the control unit and connect it to the data-path with correct labeling. ​ ​
Q3. Consider C-like code provided below.

Inputs: bit start, bit op1; uint32_t x;


Outputs: bit done; uint32_t result;

while (1) {
while (!start);
done = 0;

if (op1) result = x * 2;
else result = x;

while (x > 0) {
if (op1) result = result / 2;
else result = result + 1;
x--;
}
done = 1;
}

(a) Draw the High-Level State Machine for this code using the minimum possible states.
(b) Draw the datapath for the HLSM.

(c) Connect datapath to control and show all signals going in/out of both.
Q4. Design a lookup table with 20x8 bits for the sequence below:

● Q(1) = 1, Q(2) = 3​
● For n > 2, Q(n) = Q(n-1) +2*(n % 4)

(% is the modulo operator, giving the remainder after division. e.g., 7 % 4 = 3)​
● n < 20​
● When A=1 and B=1, a new term is added. If A=1 and B=0, the last term is removed.​
If the table is fully filled, D=1.​
● All terms are stored in a memory that can hold 20 8-bit elements. Each memory element can
be accessed with the index "i"

(a) Draw the High-level State Machine to represent the behavior of this system.

(b) Draw the datapath for this system.

​
(c) Draw the connections from the datapath to the controller.

(d) Draw the FSM State Diagram for the controller to this datapath.

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