Op-amps as Half wave & Full wave Rectifiers

The rectifier converts AC to DC, but in a precision rectifier we use an

op-amp to compensate for the voltage drop across the diode, that is why
we are not losing the 0.6V or 0.7V voltage drop across the diode, also the
circuit can be constructed to have some gain at the output of the amplifier
as well.

when the input signal is negative, the output will be zero volts and when the
input signal is positive the output will follow the input signal.
In the above rectifier circuit, the output waveform will be 0.7 volts less than the
applied input voltage, And, the diode will only conduct if the applied input signal
is slightly greater than the forward voltage of the diode.
the circuit diagram of a half wave rectifier shown above looks like an inverting
amplifier, with two diodes D1 and D2 in addition.

The working of the half wave rectifier circuit shown above is explained below

​ For the positive half cycle of the sinusoidal input, Diode D1 conducts
causing output voltage to go negative by one voltage drop (-0.6 or -0.7)
Hence diode D2 will be reverse biased. Hence, the output voltage of the
above circuit is zero volts, since no current flows through Rf.
​ For the negative half cycle of sinusoidal input, D1 is off, D2 ON.the
output of the op-amp will be positive. So, the output voltage of above
circuit will be

Therefore, the output of a half wave rectifier will be a positive half cycle
for a negative half cycle of the sinusoidal input. Input /output waveforms are
shown below:
The op -amp in the
The above circuit diagram consists of two op-amps, two diodes, D1 & D2 and five
resistors, R1 to R5. The working of the full wave rectifier circuit shown above is
explained below −

​ For the positive half cycle of a sinusoidal input, the output of the first
op-amp will be negative. Hence, diodes D1 and D2 will be forward biased
and reverse biased respectively.
​ Then, the output voltage of the first op-amp will be −
​
​ Observe that the output of the first op-amp is connected to a resistor R4,
which is connected to the inverting terminal of the second op-amp. The
voltage present at the non-inverting terminal of second op-amp is 0 V. So,
the second op-amp with resistors, R4 and R5 acts as an inverting
amplifier.
​ The output voltage of the second op-amp will be

​
​ Substituting the value of V01 in the above equation, we get

​
​ Therefore, the output of a full wave rectifier will be a positive half cycle
for the positive half cycle of sinusoidal input. In this case, the gain of the
output is R2R5/R1R4. If we consider
​ R1=R2=R4=R5=R, then the gain of the output will be one.
​ For the negative half cycle of a sinusoidal input, the output of the first
op-amp will be positive. Hence, diodes D1 and D2 will be reverse biased
and forward biased respectively.
​ The output voltage of the first op-amp will be

Since Vi in the above equation is -ve

half cycle, final output is +ve.
​ The output of the first op-amp is directly connected to the non-inverting
terminal of the second op-amp. Now, the second op-amp with resistors,
R4 and R5 acts as a non-inverting amplifier.
​ The output voltage of the second op-amp will be −
​ V0=(1+R5/R4)V01
​
​ The input and output waveforms of a full wave rectifier are shown in
the following figure
As you can see in the above figure, the full wave rectifier circuit diagram that
we considered will produce only positive half cycles for both positive and
negative half cycles of a sinusoidal input.

Peak Detector Circuit is used to find the peak amplitude in a rapidly changing
waveform. Peak detectors are generally used in the sound measuring
applications to find the maximum level of sound in a particular area or place, that
helps in determining the maximum loudness level in that place. A Simple Peak
Detector Circuit can be built by using a diode and a capacitor.
In the positive half cycle of the signal, the diode will be forward biased and
allows the current to pass through it. At the same time, the capacitor starts
charging to the peak value of the input signal until the diode remains forward
biased.

Now, in the negative half cycle of the signal, the diode gets reverse biased and at
that time the capacitor holds the peak value of the previous half cycle. Hence,
this is called as Peak Detector and the output waveform will look like the image
given below,
Practically the output is taken across some load connected to the circuit. So,
when the input signal is decreasing the capacitor starts discharging through the
load RL. To hold the charge and slow down the discharging of capacitor choose
the load RL of very high value.

The output of the circuit will be defined as

VOUT = VIN - VD

Where VIN is the input signal voltage and VD is the voltage drop across the diode.
Here, in the output waveform, you can see the peak is shifted down because of
the voltage drop across the diode in the circuit. So, this voltage drop at diode
reduces the efficiency of the circuit, and to improve the design next we will use
Op-amp.

For detecting the negative peak of the input signal connect the diode in the
reverse condition.

Op-amp based Peak Detector Circuit

An operational amplifier (op-amp) can be incorporated into a peak detector
circuit to enhance its performance. The op-amp-based peak detector offers
higher precision and faster response times. The op-amp acts as a buffer and
improves the stability of the circuit. Here's a simplified diagram of a Peak
detector using an op-amp

Op-amp based peak detector circuit is the modification of basic peak detector
circuit, used to remove the voltage drop across the diode. Whenever the applied
input voltage signal is greater than the threshold voltage of the diode, the diode
will get forward biased and acts as a closed switch. Here, the diode is connected
in the feedback and hence the circuit works as a buffer circuit. So, whatever input
is applied to the positive terminal of the op-amp will be received at the output
terminal.

Circuit Diagram
Working of the Op-amp based Peak Detector Circuit
In the first positive half cycle, the op-amp output is HIGH, so the diode is forward
biased. At the same time, the capacitor charges to the highest peak value of the
input signal. Here, the circuit is working as a voltage follower buffer circuit.

In the first negative half cycle, the op-amp output is LOW so the diode will be
reversed biased. Therefore, until the diode again gets forward biased the
capacitor holds the peak value of the input signal. In this reverse biased
condition of the diode, the op-amp is in open loop condition and goes into
saturation, so the capacitor starts discharging into the RL. That’s why you will see
the decreasing slope in the negative cycle of the signal.

The output waveform of the op-amp based peak detector circuit is given below:
Material Required
●​ Oscilloscope
●​ LM741- Op-amp IC
●​ Diode - 1N4007
●​ Resistor (10k) - 3nos.
●​ Capacitor (4.7uf) - 1nos.
●​ Breadboard
●​ Wires
Sample & Hold Circuit:
A sample & hold circuit samples an input signal and holds on to its last
sampled value until the input is sampled again.
Sampling : Process of converting a continuous signal to discrete samples or
pulses, which may or may not be uniformly spaced in time is called sampling .
The time gap between first sample & second sample is called Sampling Time
Ts. I/Ts is called sampling frequency.
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A Sample and Hold circuit consist of switching devices, capacitor and
an operational amplifier. Capacitor is the heart of the Sample and
Hold Circuit because it is the one who holds the sampled input signal
and provide it at output according to command input. This circuit is
mostly used in Analog to Digital Converters to remove certain
variations in input signal, which may corrupt conversion process.

A typical block diagram of Sample and hold circuit is mentioned

below:

Generally applied input voltage signal is a continuously changing

analog signal. Command input is provided to trigger the sampling and
holding of input signal. Command input is nothing but a on/off signal
to start/stop sampling of input signal, it is generally PWM. The
sampling and holding process depends upon the command input.
When the switch is closed the signal is sampled and when its open ,the
circuit holds the output signal. The On/OFF condition of switch is
controlled by command input.

The ideal input and output waveform of the sample and hold
circuit is given below:

can be clearly understood from the above diagram that this circuit
takes samples of input signal for the time Command Input is high and
replicate the same sample at the output. And when the command
input is LOW, it keeps the last voltage level of sampled signal.
The below circuit diagram shows the sample and hold circuit with the help of

an Op-Amp. It is plain from the circuit diagram that two op-amps are linked

through a switch. When the switch is locked sampling method will come into

the image and when the switch is unlocked holding outcome will be there. The

capacitor allied to the second op-amp is nothing but a holding capacitor.

MOSFET acts as a switch and is controlled by the control voltage and
capacitor stores the charge. Analog signal to be sampled is applied to drain
of MOSFET and control voltage is applied to gate of MOSFET.

When control voltage is positive, MOSFET turns ON, and capacitor C

charges to the instantaneous value of input Vi with a time constant
[(Ro+rDS(on)]C.

Ro is output resistance of the voltage follower A1&rDS(on) → resistance of

MOSFET when on.Thus input voltage appears across the capacitor and
then at the output through the voltage follower A2.

During the time when control voltage is zero, MOSFET is off. Capacitor C is
facing now high input impedance of the voltage follower A2 and cannot
discharge. The capacitor holds the voltage across it.

Time period Ts , the time during which voltage across the capacitor is equal
to the input voltage is called sample period. Time period TH during which
the voltage across the capacitor is held constant is called hold period.
Frequency of control voltage should be kept higher than(at least twice) the
input , so as to retrieve input from output waveform.

Some Applications of Sample and Hold Circuit

●​ ADCs (Analog-to-Digital Conversion)
●​ DACs (Digital-to-Analog Conversion)
●​ In Analog Demultiplexing
●​ In Linear Systems
●​ In Data Distribution System
●​ In Digital Voltmeters
●​ In Signal Constructional Filters
PHASE LOCKED LOOP:
A phase-locked loop (PLL) is an electronic circuit with a voltage or voltage-driven
oscillator that constantly adjusts to match the frequency of an input signal. PLLs are
used to generate, stabilize, modulate, demodulate, filter or recover a signal from a
"noisy" communications channel where data has been interrupted.
It can also be stated that PLL is a feedback control system that automatically
adjusts the phase of a locally generated signal to match the phase of an input signal.
PLLs operate by producing an oscillator frequency to match the frequency of an input
signal.
Phase Locked Loop (PLL) is one of the vital blocks in linear systems. It is useful
in communication systems such as radars, satellites, FMs, etc.

Working Principle of PLL:

In a PLL, the two inputs of the phase detector are the reference input and the feedback
from the VCO. The PD output voltage is used to control the VCO such that the phase
difference between the two inputs is held constant, making it a negative feedback
system.

Block Diagram of PLL

A Phase Locked Loop (PLL) mainly consists of the following three blocks −

​ Phase Detector
​ Active Low Pass Filter
​ Voltage Controlled Oscillator (VCO)

The block diagram of PLL is shown in the following figure −

The output of a phase detector is applied as an input of active low pass filter.
Similarly, the output of active low pass filter is applied as an input of VCO.

The working of a PLL is as follows −

VCO is a free running multivibrator and operates at a set frequency fo called
free running frequency. This frequency is determined by an external timing
capacitor and an external resistor. It can also be shifted to either side by
applying a dc control voltage Vc to an appropriate terminal of IC. Frequency
deviation is directly proportional to the dc control voltage and hence it is called
a “Voltage Controlled Oscillator”

​ The phase detector in a PLL is actually a phase difference detector

​ Phase detector produces a DC voltage, which is proportional to the
phase difference between the input signal having frequency of
​ Fin and feedback (output) signal having frequency of fout.
​ A Phase detector is a multiplier and it produces two frequency
components at its output − sum of the frequencies
​ fin and fout and difference of frequencies fin & fout.
​
​ The output of the phase detector is not a straightforward analog signal
that is proportional to the phase difference. The straightforward analog
signal is in there somewhere, but it’s combined with high-frequency
content that makes the signal look very different from what we might
expect. Hence the low-pass filter: it suppresses the higher-frequency
components(sum frequency component), difference frequency component
is amplified and then applied as control voltage Vc to VCO. The signal Vc
shifts the VCO frequency in a direction to reduce the frequency difference
between fin and fout. Once this action starts, we say that the signal is in
capture range.
​ VCO continues to change frequency till its output frequency is exactly the
same as the input signal frequency. The circuit is then said to be locked.
​ Once locked, output frequency fo of VCO is identical to fin except for a
finite phase difference ⲫ. This phase difference generates a corrective
control voltage to shift the VCO frequency from fout to fin and thereby
maintain the lock.

​
​ An active low pass filter produces a DC voltage at its output, after
eliminating high frequency component present in the output of the phase
detector. It also amplifies the signal.
​
 ​ The voltage-controlled oscillator is, an oscillator controlled by a voltage.
More specifically, the frequency of the periodic signal generated by the
oscillator is controlled by a voltage. So the VCO is a variable-frequency
oscillator that allows an external voltage to influence its frequency of
oscillation. In the case of a PLL, the control voltage is a low-pass-filtered
phase-detector signal.
​

The above operations take place until the VCO frequency equals to the input
signal frequency. Based on the type of application, we can use either the output
of active low pass filter or output of a VCO. PLLs are used in many applications
such as FM demodulator, clock generator etc.

PLL operates in one of the following three modes −

​ Free running mode

​ Capture mode
​ Lock mode

Initially, PLL operates in free running mode when no input is applied to it.
When an input signal having some frequency is applied to PLL, then the output
signal frequency of VCO will start change. At this stage, the PLL is said to be
operating in the capture mode. The output signal frequency of VCO will change
continuously until it is equal to the input signal frequency. Now, it is said to be
PLL is operating in the lock mode.

IC 565
IC 565 is the most commonly used phase locked loop IC. It is a 14 pin
Dual-Inline Package (DIP). The pin diagram of IC 565 is shown in the following
figure −
The purpose of each pin is self-explanatory from the above diagram. Out of 14
pins, only 10 pins (pin number 1 to 10) are utilized for the operation of PLL. So,
the remaining 4 pins (pin number 11 to 14) are labelled with NC (No
Connection).

The VCO produces an output at pin number 4 of IC 565, when the pin numbers
2 and 3 are grounded. Mathematically, we can write the output frequency,

fout of the VCO as.

fout=0.25/RVCV

where,

RVis the external resistor that is connected to the pin number 8

CVis the external capacitor that is connected to the pin number 9

​ By choosing proper values of RV and CV, we can fix (determine) the output
frequency, fout of VCO.
 ​ Pin numbers 4 and 5are to be shorted with an external wire so that the
output of VCO can be applied as one of the inputs of phase detector.
​ IC 565 has an internal resistance of 3.6KΩ. A capacitor, C has to be
connected between pin numbers 7 and 10 in order to make a low pass
filter with that internal resistance.

Note that as per the requirement, we have to properly configure the pins of IC
565.

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