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CSE460-03L Assignment-1

The document outlines a lab assignment for a VLSI Design course at BRAC University, focusing on designing, implementing, and simulating a 4-bit up/down counter in Verilog. It includes specifications for inputs, outputs, and behavior of the counter, as well as a second task involving the creation of functions based on sensor inputs. Students are required to submit a PDF file containing their Verilog code and simulation results by December 1st, 2024.

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3 views3 pages

CSE460-03L Assignment-1

The document outlines a lab assignment for a VLSI Design course at BRAC University, focusing on designing, implementing, and simulating a 4-bit up/down counter in Verilog. It includes specifications for inputs, outputs, and behavior of the counter, as well as a second task involving the creation of functions based on sensor inputs. Students are required to submit a PDF file containing their Verilog code and simulation results by December 1st, 2024.

Uploaded by

shayonto.rayhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BRAC UNIVERSITY

VLSI DESIGN
CSE460
Lab Assignment 1, Section 3
Fall 2024
Marks:

Answer all the questions.


Deadline: 1st December, 11:59 pm
File name: ID.pdf

Task 1: Design, Implement, and Simulate a 4-Bit Up/Down Counter in Verilog

Objective:

The goal of this task is to design a 4-bit up/down counter in Verilog, write the Verilog code, and
validate its functionality through simulation.

Specifications:

1. Inputs:
○ R [3:0]: A parallel load input. This represents the value to be loaded into the
counter when the load signal is active.
○ Resetn: An asynchronous reset signal. When this signal is low (Resetn = 0),
the counter is reset to 0.
○ Clock: A clock signal to drive the counter operations.
○ E: An enable signal. When this signal is high (E = 1), the counter is enabled for
counting.
○ L: A load signal. When this signal is high (L = 1), the value of R is loaded into
the counter.
○ up_down: A control signal to determine the counting direction:
■ up_down = 1: The counter counts up.
■ up_down = 0: The counter counts down.
2. Outputs:
○ Q [3:0]: The current value of the counter.
3. Behavior:
○ When Resetn = 0: The counter is reset asynchronously to 0.
○ When L = 1: The counter loads the value of R into Q on the rising edge of the
clock.
○ When L = 0 and E = 1:
■ If up_down = 1: The counter counts up on the rising edge of the clock.
■ If up_down = 0: The counter counts down on the rising edge of the
clock.

Task Requirements:

1. Write the Verilog Code:


○ Implement a parameterized Verilog module for the 4-bit up/down counter based
on the specifications provided.
2. Simulate and Analyze:
○ Simulate the design and test for the following cases:
■ Asynchronous reset (Resetn).
■ Parallel loading (L = 1).
■ Counting up and down with the up_down signal.
○ Generate waveform results to demonstrate the behavior of the counter.
○ Include the following signals in the waveform: Resetn, Clock, E, L, R, up_down,
and Q.
Task 2:

Suppose you have 4 sensors. Based on the input from these sensors, you must build 5
separate functions.

Function Condition to be high


f1 All sensors are high

f2 Any one of the sensors is high

f3 An even number of sensors are high

f4 Exactly 4 sensors are high

f5 Less than 2 sensors are high

Task Requirements:

1. Find the expressions for each function. You can use K-map or Boolean.
2. Write a verilog code to implement the functions. You are only allowed to use one input
variable and one output variable. [Hint: Look into arrays]
3. Generate the timing diagram for the functions. Make sure to show all possible cases.

Submit a pdf file that contains all the requirements for both tasks.

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